Completed my first Virtex4 design

Started by Philip Freidin in comp.arch.fpga13 years ago 5 replies

Well, Xilinx shipped me my Foundation 6.3i software update, and since it has the initial support for Virtex 4, I installed it and did a...

Well, Xilinx shipped me my Foundation 6.3i software update, and since it has the initial support for Virtex 4, I installed it and did a design. Here it is: ==== module top(in_bus,out_bus); input [15:0] in_bus; output [15:0] out_bus; assign out_bus = {in_bus[14:0],in_bus[15]}; endmodule ==== Par Report (trimmed): Release 6.3i Par G.35 Copyright (c) 1995-2004 Xi...


Virtex4: Usign OSERDES + LVDS Deserializers

Started by Roel in comp.arch.fpga13 years ago 4 replies

Hi Has someone experience in using the OSERDES in combination with a commercial Deserializers like MAX9206/MAX9208 or SCAN921226 ? I was...

Hi Has someone experience in using the OSERDES in combination with a commercial Deserializers like MAX9206/MAX9208 or SCAN921226 ? I was wondering whether it would be possible to meet the jitter requirements and thereby preventing that the deserializer's PLL unlocks. I can' find the right information for this in the Virtex-4 DC and Switching Characteristics. To generate e.g. 500Mb/s o...


virtex4 virtex-4 FX eval board

Started by Pete in comp.arch.fpga13 years ago 2 replies

Hello Is there a Virtex4 FX eval board available yet? We want to begin working with the on-chip Gig Ethernet mac. Pete

Hello Is there a Virtex4 FX eval board available yet? We want to begin working with the on-chip Gig Ethernet mac. Pete


Virtex 4 USER1 ~ USER4 JTAG commands

Started by Anonymous in comp.arch.fpga13 years ago 3 replies

Hello everyone, I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software. I have used my...

Hello everyone, I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software. I have used my software to access such USER1, USER2 commands in previous generation FPGAs such as Virtex-II. Virtex 4 uses different JTAG command bit patterns (10 bit long) and I changed the table so that JTAG commands to be issued have the correct JTAG command bit...


Chipscope and Virtex4 LX25 ES

Started by John Williams in comp.arch.fpga13 years ago 1 reply

Hi, Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES parts and the JTAG chains, with workarounds for the EDK's XMD and...

Hi, Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES parts and the JTAG chains, with workarounds for the EDK's XMD and opb_mdm tools. However, this silicon bug also affects ChipScope Pro, but no solution is offered. We are considering prototyping a large project on the ML401 (which uses V4-LX25 ES parts), but ChipScope support will be essential. Does anybody ha...


Connecting Virtex2pro to Virtex4 via RocketIO MGT's

Started by jason.stubbs in comp.arch.fpga13 years ago 5 replies

The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virtex-4 also serializes...

The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virtex-4 also serializes and sends the least significant byte first. This is opposite of the format Virtex-II Pro devices used in sending the most significant byte first./* What does this really mean? Are the v2pro and v4 MGT's incompatible because of this? Will it wor...


Virtex4 running at 360Mhz DDR

Started by Anonymous in comp.arch.fpga13 years ago 40 replies

I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like hear what others think...

I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like hear what others think and perhaps point out where I need to be careful in the design. I'd be receiving an LVDS clock pair @ 360Mhz, running part of the internal logic at 360. This internal logic includes DSP48 slices (but need to be pipelined in the fabric since I need m...


virtex 4 configuration error

Started by Anonymous in comp.arch.fpga12 years ago

Hello. I am trying to use the ML402 virtex4 (SX35) board and facing some problems getting the FPGA to configure. I dont have a PC4...

Hello. I am trying to use the ML402 virtex4 (SX35) board and facing some problems getting the FPGA to configure. I dont have a PC4 programming cable, and am using the System ACE to do it for me. After i generate a Bitstream (no errors), i put it on the Compact flash and let the system ace program it to the linear (CPLD) flash using the flah programming bitstream provided in the board dem...


Virtex4 : Downloading error

Started by Shakith in comp.arch.fpga12 years ago 1 reply

I created microblaze design using bases system builder for virtex 4 lx25 lc board using Xilinx EDK 7.1i sp2. After downloading, when using xmd...

I created microblaze design using bases system builder for virtex 4 lx25 lc board using Xilinx EDK 7.1i sp2. After downloading, when using xmd to connect, the following error happens.. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0167c093 10 XC4VLX25 Assuming, Device No: 1 contains the MicroBlaze system WARNING:EDK - MDM Per...


Virtex4 temperature-sensing feature... does it work?

Started by I. Ulises Hernandez in comp.arch.fpga12 years ago 5 replies

Hello guys, Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the results were all right, what external sensor did you...

Hello guys, Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the results were all right, what external sensor did you use...? Thanks in advance, -- Ignacio Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O)


Virtex 4 desing : ChipScope insertion impacts my timing problem debug

Started by Anonymous in comp.arch.fpga12 years ago 2 replies

Hi, I am working on a Virtex4 FX design, when the system clock runs at 100MHz, the memory controller core does not work correctly. Then...

Hi, I am working on a Virtex4 FX design, when the system clock runs at 100MHz, the memory controller core does not work correctly. Then I inserted ChipScope trying to identify the problem, but once it is inserted, the problem is gone! I know it is of timing problem since if I lower the system clock to 50MHz, there is no problem either. It looks like that after the chipscope is ins...


Virtex4 : Audio Codec AC97 LM4550

Started by Lori Lorenser in comp.arch.fpga12 years ago 2 replies

Hi. I'm working with the Virtex 4 on a ML403 and want to use the audio codec AC97. At first i want to connect a mp3-player to line in and then...

Hi. I'm working with the Virtex 4 on a ML403 and want to use the audio codec AC97. At first i want to connect a mp3-player to line in and then i want to manipulate the audiostream and send it to line out. But i don't find a detailled description (e.g not in ml403 userguide) of the audio codec. So i don't know which pin i should use. Does anybody know a paper/tutorial/user guide or something ...


Virtex4 MGTs using Aurora Core

Started by Anonymous in comp.arch.fpga12 years ago

Hi, I am having problems trying to get an Aurora core working in Virtex 4 parts. Has anyone managed to get an MGT working in Virtex4? I am...

Hi, I am having problems trying to get an Aurora core working in Virtex 4 parts. Has anyone managed to get an MGT working in Virtex4? I am using Aurora 2.4 and just trying to do a simple loopback between 2 MGTs. I can't get CHANNEL_UP to assert in the Aurora cores and the MGT is showing RXBUFERR indicating an RX FIFO underflow/overflow? I have followed all the clocking recommendations...


Virtex 4 deconfiguring itself ...

Started by Sylvain Munaut in comp.arch.fpga12 years ago 3 replies

Hello, We're currently working on a design running on a Virtex4 SX35. That design uses most of the resources of the FPGA (around 80% of the...

Hello, We're currently working on a design running on a Virtex4 SX35. That design uses most of the resources of the FPGA (around 80% of the slices and 50% or the BRAMs/multipliers). We're working on the AVNET SX35 kit with a VGA extension card and a sdram expension card. Depending of the datafiles we send, sometimes it completly deconfigure the FPGA ... done goes de-asserted and nothing ...


Virtex4 FX12 dynamic clock divider

Started by Guru in comp.arch.fpga12 years ago 12 replies

Hi everyone, For my design, which is implemented in Virtex-4 FX12 (speed grade -10) I need to get an adjustable (in operation) clock of...

Hi everyone, For my design, which is implemented in Virtex-4 FX12 (speed grade -10) I need to get an adjustable (in operation) clock of frequency 30 to 66 MHz with the smallest possible increments. On the board I have 100MHz oscillator from which I tried to get 400 MHz (the higher the frequency the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX 4/1). From this DCM I als...


Virtex 4 ACE Compact Flash configuration problem

Started by Dan in comp.arch.fpga11 years ago 25 replies

I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn the device on the red LED...

I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn the device on the red LED 'Err' turns on.


Linear priority encoder in Xilinx Virtex4

Started by Sylvain Munaut in comp.arch.fpga11 years ago 4 replies

Hello, I need a linear priority encoder that has N input and N outputs. Searching the group, I saw a thread where Peter Alfke stated : ---...

Hello, I need a linear priority encoder that has N input and N outputs. Searching the group, I saw a thread where Peter Alfke stated : --- cut --- > Let me tell you what can be done in Virtex-4 (probably also in > Spartan3): > A priority "linear encoder" with 4 x N inputs and 4 x N outputs, each > output corresponding to a prioritized input. > Only one output is ever active, the one


Location of Virtex4 ASCII pinout tables

Started by Anonymous in comp.arch.fpga11 years ago 4 replies

I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under "Products") This brings up the...

I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under "Products") This brings up the URL http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/index.htm At this URL, on the right, under "Related Information", there is a link named "Virtex-4 package files" The actual URL this link points to is http://www.xilinx.com/products/virtex4/virtex-4-pkgs.htm ...


Virtex-4 configuration details

Started by jbnote in comp.arch.fpga11 years ago

Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4. My reference point...

Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4. My reference point is the virtex-2 configuration. In the virtex-2 configuration, FDRI writes always include a pad frame (except in the MFWR write case, but that's not what i'm looking at). Virtex-4 documentation makes no hint at such a frame. Indeed, uncompressed bi...


Supported bus widths for RLDRAM on Virtex4?

Started by Your name in comp.arch.fpga11 years ago 1 reply

Hi there, I'm trying to decide on which FPGA vendor to use for a project out of Xilinx and Altera. The one we chose will depend on a certain...

Hi there, I'm trying to decide on which FPGA vendor to use for a project out of Xilinx and Altera. The one we chose will depend on a certain memory bandwidth being met so I'm interested in the maximum supported bus widths. I'm currently heading down the RLDRAM route and have been trying to figure out how many devices are supported on the larger Virtex-4 devices. Does anyone have an...