Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)

Started by Bruce in comp.arch.fpga13 years ago 2 replies

Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant...

Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant to the Infiniband standard (beacon and variant CRC excluded). There are two types of CRC, the invariant and the variant type. Although the RocketIOs are able to calculate at least one type, i.e. the invariant CRC, you cannot make use of it in this par...


How do I make use of local-clocks in a Virtex-2 FPGA?

Started by Kelv...@ SG in comp.arch.fpga14 years ago 1 reply

Hi, there: I saw this statement in Virtex-2 datasheet, how do I make use of these local clocks? Is there any documents on these local...

Hi, there: I saw this statement in Virtex-2 datasheet, how do I make use of these local clocks? Is there any documents on these local clocks? Best Regards, Kelvin Local Clocking In addition to global clocks, there are local clock resources in the Virtex-II devices. There are more than 72 local clocks in the Virtex-II family. These resources can be used for many different applic...


Virtex 2 Fastest MUX performance

Started by Adam in comp.arch.fpga13 years ago 1 reply

On the bottom of page 7 of the Virtex II DC and Switching Characteristics datasheet, a table shows that register-to-register performance of a 4:1...

On the bottom of page 7 of the Virtex II DC and Switching Characteristics datasheet, a table shows that register-to-register performance of a 4:1 mux can reach 563 MHz. I'm just curious exactly how this was measured. Thanks, Adam


Virtex2 (500) DCM Frequency Synthesize

Started by Jerzy in comp.arch.fpga13 years ago 3 replies

Hello I've got following problem: I need 27MHz and 54MHz clocks, input freq. is 20MHz. Till today I used DCM FS 27/20 next to DLL and...

Hello I've got following problem: I need 27MHz and 54MHz clocks, input freq. is 20MHz. Till today I used DCM FS 27/20 next to DLL and DLL*2. Theoreticly it should works OK, but doesn't. From time to time after reboot or after clok stop, it works strange and completly bad. Today I've read about jitter on output of DCM's CLKFX, I check on "Virtex-II CLKFX Jitter Calculator" that in this condi...


Virtex II LVDS plus DDR?

Started by Mark in comp.arch.fpga13 years ago 1 reply

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear...

Howdy Gurus, I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear explanation yet of the two being used together. DDR by itself is pretty obvious, but the LVDS appears to work by a magical connection between two neighboring IOBs. For an LVDS input pair (Dp and Dn) coming in at DDR, does the differential-to-single-ended ...


Virtex2 I/O standards

Started by gja in comp.arch.fpga13 years ago 3 replies

For Virtex II parts, I see that the Vih and Vil levels are the same for LVTTL and LVCMOS33, my question is are the input structures really...

For Virtex II parts, I see that the Vih and Vil levels are the same for LVTTL and LVCMOS33, my question is are the input structures really different or are they the same for the two standards. Also, are the output structures for LVTTL the same as LVCMOS33, since both Vol are the same, and LVTTL Voh is a subset of LVCMOS33 Voh.


DDR SODIMM on Avnet Virtex II PRO development kit

Started by ZioPino in comp.arch.fpga12 years ago 20 replies

Hi all, I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO development kit from Avnet, with a XC2VP20 onboard), and I was...

Hi all, I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO development kit from Avnet, with a XC2VP20 onboard), and I was wondering if it was possible to connect the DDR SODIMM module (the board comes with a Micron 128 MB module) to a Xilinx EDK 6.3 design with plb_ddr or opb_ddr IP. In fact the UCF that came with the board support package lack of any reference to a DDR cl...


Simulation problems virtex II

Started by zoin...@mytrashmail.com in comp.arch.fpga12 years ago

Hi everyone, I have been trying to get a good behavioral simulation going of a Virtex2 on the ML310 board. I'm trying to simulate a standard...

Hi everyone, I have been trying to get a good behavioral simulation going of a Virtex2 on the ML310 board. I'm trying to simulate a standard generated chip architecture with DSOCM & ISOCM running the standard generated test-program. As far as I know there are two ways to go (with the software I have): 1) directly from XPS 2) via ProjectNavigator The problem with 1) is tha...


virtex II global buffer

Started by zora in comp.arch.fpga12 years ago 1 reply

Hi I need to use more than 8 global buffer in a virtex II design. I know that VirtexII supports up to 16 Global Buffer divided in more clock...

Hi I need to use more than 8 global buffer in a virtex II design. I know that VirtexII supports up to 16 Global Buffer divided in more clock regions, but ISE PAR doesn't automatically divide project in two (or more) clock region and it uses only 8 global buffer. How can I use the other global buffer?


Virtex 2 configuration problem

Started by gja in comp.arch.fpga12 years ago 2 replies

I'm looking for some suggestions as to what else to look at to fix this problem: Using a Virtex II xc2v40 and xcf02s prom connected in master...

I'm looking for some suggestions as to what else to look at to fix this problem: Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode. JTAG is also implemented. We've built around 50 of these boards without this problem so I believe it's just this particular board. It intermittently doesn't configure on power up. A power chip holds INIT_B low until 3.3v is 3v to...


Virtex2: can I really just leave M1,M2,M3 pins floating?

Started by ML in comp.arch.fpga11 years ago 1 reply

Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1, M2, M3 pins floating or is it safer to tie them to VCCaux ? ML

Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1, M2, M3 pins floating or is it safer to tie them to VCCaux ? ML


Files.ucf QAM Demodulators for Xtreme DSP Development KIT

Started by vlir_c8 in comp.arch.fpga11 years ago

Hello everyboby, My name is Giovanny I am working with two types of xtreme dsp Development cards: Kit virtexII ( xc2v3000) and virtex...

Hello everyboby, My name is Giovanny I am working with two types of xtreme dsp Development cards: Kit virtexII ( xc2v3000) and virtex II PRO (xc2vp30) ; I am trying to implement the example "16 QAM demodulator for Software Defined Radio" running sysgenqam16_dplr.mdl file in simulink ;I have been using the tool "system generator" for generating VHDL code , but I have realized that...


virtex II inner organisation

Started by flo in comp.arch.fpga11 years ago 4 replies

Hi everyone, I'm trying to deal with readback and scrubbing into a XC2V1500 FPGA. I've got a problem identifying the Major Adress and the...

Hi everyone, I'm trying to deal with readback and scrubbing into a XC2V1500 FPGA. I've got a problem identifying the Major Adress and the Minor Adress when I'm doing a readback. I read documents (XAPP138 and XAPP151) but nothing works with virtexII. I know the frame length and the number of frame because it is in the bitstream but nothing about the number of frame in each minor adress ...


problems with IOSTANDARD

Started by Martin Geisse in comp.arch.fpga11 years ago 10 replies

Hi to all, I'm trying to set the output voltage level of a Virtex 2 pro using the IOSTANDARD constraint, but it doesn't work. More exactly,...

Hi to all, I'm trying to set the output voltage level of a Virtex 2 pro using the IOSTANDARD constraint, but it doesn't work. More exactly, I'm using the XUP Virtex-II Pro Development System (an evaluation board) by Xilinx. For an application, I need the FPGA to output 3.3 V signals on the left low-speed expansion connector. I have tried to achieve this by placing the following lines in ...


Unisim versus Virtex2 Xilinx Library

Started by Pablo in comp.arch.fpga10 years ago

Hi, I have seen a piece of code in which there is elements such as FDP, BUFG and DCM. This code is to get different clocks from...

Hi, I have seen a piece of code in which there is elements such as FDP, BUFG and DCM. This code is to get different clocks from internal reference clock. I have simulated this but I cannot. These elements uses virtex2.FDP, virtex2.BUFG, ... so library virtex2 is used. My board is Virtex II Pro, so could I use this library?. I suppose that yes. My question is about unisim and virtex2. ...


its regarding to the Max Frequency in xilinx FPGA

Started by Anonymous in comp.arch.fpga9 years ago 4 replies

Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex...

Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex series FPGA's 1. every virtex series is having maximum frequency where we can use in some of higher end applications,so virtex, virtexII, virtex-E, and virtex-II Pro all serieses are having their Max frequency based on upgradations. So xilinx will ...


Virtex 2 with PLB_v34 and EDK 10.1

Started by rmeiche in comp.arch.fpga9 years ago 2 replies

Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB shipped with the...

Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB shipped with the EDK 10.1 is the PLB_v46 which doesn't support the virtex II, only V2Pro and V4. At the datasheets on the xilinx website I found that the PLB_v34 should support the V2 (see this link: http://www.xilinx.com/products/ipcenter/plb_v34.htm ). But there...


DISABLING POWERPC IN VIRTEXII PRO

Started by ni in comp.arch.fpga9 years ago 2 replies

I have AMIRIX ap1070 board with a xilinx virtex II PRO XC2VP70 . I am trying to use it for network based application . I am not using...

I have AMIRIX ap1070 board with a xilinx virtex II PRO XC2VP70 . I am trying to use it for network based application . I am not using the powerpc at all and was wondering if there is a way to disable the powerpcs and the plb/opb buses on the chip. There is a pci bridge from tundra on board which helps in pci communication with the host. I dont knwo if I would be able to configure it using the...


Virtex 2 Pro IO Banks Vcco

Started by Manfred in comp.arch.fpga8 years ago 4 replies

Hi all, I'm having the following problem: I'm trying to interface a XUP Virtex-II Pro Development System with a CMOS camera, and the output...

Hi all, I'm having the following problem: I'm trying to interface a XUP Virtex-II Pro Development System with a CMOS camera, and the output voltage on the board's expansion connectors is 2.5V for logic '1', no matter what IOSTANDARD is specified in the ucf file. I understand this is because the Vcco for the io bank is 2.5V. (However, in the schematic it shows that for the IO Banks that relate to ...


Xilinx price question

Started by Anonymous in comp.arch.fpga14 years ago

Hi, I've just had a look at marshall's (avnet) web site and it seems that the Xilinx Virtex II XC2VP100 is $11512. Did I miss something or lost...

Hi, I've just had a look at marshall's (avnet) web site and it seems that the Xilinx Virtex II XC2VP100 is $11512. Did I miss something or lost some zeroes ? Is it that kind of price ? Thanks a lot for your comments St?phane