its regarding to the Max Frequency in xilinx FPGA

Started by Anonymous in comp.arch.fpga13 years ago 4 replies

Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex...

Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex series FPGA's 1. every virtex series is having maximum frequency where we can use in some of higher end applications,so virtex, virtexII, virtex-E, and virtex-II Pro all serieses are having their Max frequency based on upgradations. So xilinx will ...


Virtex-3 PRO

Started by Manfred Kraus in comp.arch.fpga17 years ago 4 replies

I heard rumours XILINX will announce Virtex-3 later this year, but a VIRTEX-3 PRO is not planned. Will FPGAs with integrated Processors share...

I heard rumours XILINX will announce Virtex-3 later this year, but a VIRTEX-3 PRO is not planned. Will FPGAs with integrated Processors share the destiny of the X6200 series ?


help needed for Virtex-4

Started by saad in comp.arch.fpga13 years ago 1 reply

Hello All. Can anyone tell me the Push buttons ,leds names that i can write in the constraint file for Virtex -4. Any code that helps...

Hello All. Can anyone tell me the Push buttons ,leds names that i can write in the constraint file for Virtex -4. Any code that helps me test the functionality of virtex 4 will be appreciated.


Problem using virtex 4 and virtex 6 ibis models

Started by firefly in comp.arch.fpga9 years ago

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crystal oscillator and going...

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crystal oscillator and going to virtex 4 FPGA with part number (XC4VLX60-11FF1148) at pins AD17 and AE17 and then from vertix 4 the signal is going to Virtex 6 FPGA with part number (XC6VLX365T-FF1156) at pins G9 and H9. I downloaded IBIS models of virtex 4 and virtex 6 from the xili...


Virtex-4 Slower than V2Pro?

Started by Eric in comp.arch.fpga16 years ago 2 replies

I just got my new ISE and went straight to synthesizing some of my old designs. Basically, I'm planning on publishing soon, and figured...

I just got my new ISE and went straight to synthesizing some of my old designs. Basically, I'm planning on publishing soon, and figured the Virtex-4 would bolster my numbers even further. However, that wasn't the case. ****************************************************************** ****************************************************************** Virtex-4 Timing **********************...


Virtex II - LVDS_33_DCI?

Started by Barry Brown in comp.arch.fpga17 years ago 1 reply

In the Virtex II User Guide (v1.6.1) on pg 200, it states ... DCI in Virtex-II Hardware DCI only works with certain single-ended and...

In the Virtex II User Guide (v1.6.1) on pg 200, it states ... DCI in Virtex-II Hardware DCI only works with certain single-ended and differential I/O standards. DCI supports the following Virtex-II standards: LVDCI, LVDCI_DV2, GTL_DCI, GTLP_DCI, HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, HSTL_IV_DCI, SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI, LVDS_25, LVDSEXT_25, LVDS_33_DCI, ...


Uart core for a virtex-4

Started by Andrew Lohbihler in comp.arch.fpga15 years ago 4 replies

Hi, I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in xapp223. These are great for my Virtex-II development, and they...

Hi, I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in xapp223. These are great for my Virtex-II development, and they obviously don't work for the Virtex-4. I like the simplicity of these cores and want to change as little of my old code as possible. Does anyone know/have a free/$ replacement to these EDIF's that work for the Virtex-4? -Andrew


Virtex 4 Multiplier RPM Constraints?

Started by Love Singhal in comp.arch.fpga15 years ago 5 replies

Hi, I am trying to create a Xilinx Core Generator multiplier for Virtex 4 with RPM constraints. However, neither ISE 7.1 (IPCore 7.1) nor ISE...

Hi, I am trying to create a Xilinx Core Generator multiplier for Virtex 4 with RPM constraints. However, neither ISE 7.1 (IPCore 7.1) nor ISE 8.1 (IPCore 8.0) allows creation of Virtex 4 multiplier with RPM constraints, even if multiplier is completely LUT based. Such constraints on multiplier are allowed in Virtex 2. What is the reason for this limitation in Virtex 4? I wanted some multipl...


Connecting Virtex2pro to Virtex4 via RocketIO MGT's

Started by jason.stubbs in comp.arch.fpga16 years ago 5 replies

The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virtex-4 also serializes...

The following extract from the Virtex 4 RIO user guide states: */Serialization/* */As in Virtex-II Pro X devices, Virtex-4 also serializes and sends the least significant byte first. This is opposite of the format Virtex-II Pro devices used in sending the most significant byte first./* What does this really mean? Are the v2pro and v4 MGT's incompatible because of this? Will it wor...


Virtex-II Pro Equations for Finding a Bit Location

Started by tk in comp.arch.fpga17 years ago

Hi all, In the Xilinx Applicatoin Note 151 "Virtex Series Configuration Architecture User Guide", there are Virtex Equations for LUT SelectRAM...

Hi all, In the Xilinx Applicatoin Note 151 "Virtex Series Configuration Architecture User Guide", there are Virtex Equations for LUT SelectRAM Dependent Variables (p.11). I would like to ask are there any equations available for Virtex-II Pro ? I want to do a dynamic partial reconfiguratoin of the LUT SelectRAM. I can find out the slice position in FPGA Editor, but I can't figure out the...


Virtex II Pro, powerpc 405 and ucOSII

Started by Mancini Stephane in comp.arch.fpga17 years ago

Hi, Is there anybody ou there who tried to run the real time OS ucOSII on a virtex II platform ? Have you tried different OS ? I know that...

Hi, Is there anybody ou there who tried to run the real time OS ucOSII on a virtex II platform ? Have you tried different OS ? I know that some Virtex II Pro kits comes with Linux as embedded OS but I'm wondering if it's not too heavy for fast real time systems with dedicated hardware parts (such as image processing, etc ...). What kind of experience do you have with Virtex II Pro and diff...


JBits 3.0 and Virtex-II Pro

Started by Mahim Mishra in comp.arch.fpga16 years ago 1 reply

Hello all! I am using Xilinx Virtex-II Pro (XC2VP20 and XC2VP50) chips, and was wondering if I can use JBits 3.0 to manipulate the...

Hello all! I am using Xilinx Virtex-II Pro (XC2VP20 and XC2VP50) chips, and was wondering if I can use JBits 3.0 to manipulate the configuration bitstreams for these chips. It seems not, since the JBits "Device" class seems to only have defined constants for Virtex and Virtex-II chips. Has anyone done this before, or knows that it can be done? Thanks, Mahim


Virtex-4 configuration details

Started by jbnote in comp.arch.fpga14 years ago

Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4. My reference point...

Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4. My reference point is the virtex-2 configuration. In the virtex-2 configuration, FDRI writes always include a pad frame (except in the MFWR write case, but that's not what i'm looking at). Virtex-4 documentation makes no hint at such a frame. Indeed, uncompressed bi...


HWICAP in virtex-5

Started by fmostafa in comp.arch.fpga13 years ago 1 reply

Hi everybody, I want to ask if the HWICAP is supported and tested in Virtex-5 Boards (ML501 and ML505). I used HWICAP in Virtex -II pro and...

Hi everybody, I want to ask if the HWICAP is supported and tested in Virtex-5 Boards (ML501 and ML505). I used HWICAP in Virtex -II pro and it was working in a good way to configure certain LUTs., and i want to use Vertix-5 instead of Virtex- II pro to gain the new feature GLUTMASK (with this feature i don't have to care about the LUTs distribution ). does anyone know about this. f...


Virtex-4 FPGA with Jbits3.0?

Started by Joelmir Jose Lopes in comp.arch.fpga16 years ago

I would like to acquire the Virtex-4, however, I woul like to know which the tool that could make partial and dynami reconfigurable with such...

I would like to acquire the Virtex-4, however, I woul like to know which the tool that could make partial and dynami reconfigurable with such FPGA. Did I use JBits for Virtex, however he was not very good, does exist other tool for the Virtex-4 for partial and dynamic reconfigurabl this system? Which tool do me use for the Virtex-4 to do the partial and dynami reconfigurable? :roll: T...


reconfiguration of virtex 2 pro

Started by mani in comp.arch.fpga13 years ago

Hi friends Can u please help me in reconfiguring virtex 2 pro board... Pls give an example and steps to reconfigure virtex 2 pro.. I am...

Hi friends Can u please help me in reconfiguring virtex 2 pro board... Pls give an example and steps to reconfigure virtex 2 pro.. I am using Xilinx 8.2 i version software.. If u have some codes please send it and help me in working out reconfiguration in Virtex 2 pro ... More over how to use the xilinx 8.2i software for reconfiguration..


FFT on Virtex-II (Desperation Imminent)

Started by John Plows in comp.arch.fpga17 years ago 3 replies

Hello A collegue and I are trying to implement a 256 point FFT on a Virtex-II. The problem we are having is finding a way to transfer the...

Hello A collegue and I are trying to implement a 256 point FFT on a Virtex-II. The problem we are having is finding a way to transfer the calculated FFT data off the FPGA so we can display it (preferably in Matlab). If anyone knows of a tool for uploading/downloading to/from the block RAM on the Virtex-II, please let us know. If anyone has any information on how to interface to t...


Any Virtex 4 development/prototyping boards out there???

Started by Anonymous in comp.arch.fpga16 years ago 4 replies

Hi, I am looking for a Virtex 4 based FPGA development board with ideally a PCI Express interface and at least a FX-100 Virtex 4. If anybody...

Hi, I am looking for a Virtex 4 based FPGA development board with ideally a PCI Express interface and at least a FX-100 Virtex 4. If anybody knows of any vendors who have this or are working on this, please let me know. Thanks, Sam.


Virtex 4 configuration frames

Started by Love Singhal in comp.arch.fpga16 years ago 3 replies

Hi, We have the following questions related to Virtex 4 configuration frames: a). What is the shape and size of a frame in Virtex 4 device?...

Hi, We have the following questions related to Virtex 4 configuration frames: a). What is the shape and size of a frame in Virtex 4 device? In Virtex 2, each frame is contained in one vertical column of the device. But we could not find any information related to the shape of frame in Virtex 4. b). How many CLBs does one frame include or vice versa? c). In one datasheet, it is writ...


Virtex 4 Config

Started by maxascent in comp.arch.fpga14 years ago 4 replies

Hi Could someone just confirm for me that I can connect the config block to 3.3V in a Virtex 4 device. I have checked the data sheet and it...

Hi Could someone just confirm for me that I can connect the config block to 3.3V in a Virtex 4 device. I have checked the data sheet and it seems to indicate this. I just want to check as I have been using Virtex 2 Pro devices which need to be 2.5V. Jon