Virtex 4 : Configuration-memory readback

Started by Vivian Bessler in comp.arch.fpga15 years ago

Hi, I need to perform configuration-memory readback on an active (not shutdown) virtex 4 device. Does anyone know if on Virtex 4 is it still...

Hi, I need to perform configuration-memory readback on an active (not shutdown) virtex 4 device. Does anyone know if on Virtex 4 is it still the case that readback should not be performed on active devices, for frames that are prior to memory element frames? For Virtex 2 and Spartan 3 this can lead to configuration memory corruption. The Virtex 4 documentation is unclear on this point. Thank...


How to decode FAR register in Virtex-4?

Started by Bertrand Rousseau in comp.arch.fpga15 years ago 6 replies

Hi everyone, I'm trying to understand how the frame addresses have to be decoded for a Virtex-4 FPGA from Xilinx. So far I could find...

Hi everyone, I'm trying to understand how the frame addresses have to be decoded for a Virtex-4 FPGA from Xilinx. So far I could find documentation about the configuration for VI and VII FPGAs, but there seem to be small modifications between these models frame addresses and the new Virtex-4. Has anyone already tried to understand frame addresses in Virtex-4? Thanks Bertrand


Re: Why the second flip-flop in Virtex-6?

Started by Jan Pech in comp.arch.fpga12 years ago 1 reply

On Tue, 2009-02-03 at 15:12 +0000, Joseph H Allen wrote: > I'm surprised that the Spartan-6 integrated memory controller does not support > ...

On Tue, 2009-02-03 at 15:12 +0000, Joseph H Allen wrote: > I'm surprised that the Spartan-6 integrated memory controller does not support > DIMMs. Also surprised that there are no integrated memory controllers in > Virtex-6. > I am not. From my experience with Virtex-5 and Spartan-3 I can say that Spartans are terribly slow. If you put MPMC into Virtex-5, you can reach pretty high dat


Did National cheat with the Virtex 4

Started by lecr...@chek.com in comp.arch.fpga15 years ago 13 replies

I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly...

I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly into a Virtex 4. The videos, datasheets, etc may be found at: http://www.national.com/xilinx/ The LVDS clock coming from the ADC is 750MHz. They route this clock directly to the Virtex 4. When I look at the specs. for the Virtex 4, this would ...


Flip-flop state extraction out of reaback stream in Virtex-II/Pro

Started by Anonymous in comp.arch.fpga15 years ago 3 replies

Hi, I am dealing with reconfigurable computing and relocating modules within a Virtex-II FPGA. In order to save and restore the...

Hi, I am dealing with reconfigurable computing and relocating modules within a Virtex-II FPGA. In order to save and restore the current flip-flop states I need to determine where to find the states in a readback stream. All necessary equations were provided in xapp151, but only for the Virtex not the Virtex-II FPGAs. Given the row and column, as well as the slice and FF, I would like to know...


LVPECL_33 to LVPECL_25 (virtex-II pro)

Started by jicho in comp.arch.fpga17 years ago 2 replies

Dear all, I am trying to use differential LVPECL interface on Xilinx virtex-II pro device. I have to connect some standard LVPECL(3.3V)...

Dear all, I am trying to use differential LVPECL interface on Xilinx virtex-II pro device. I have to connect some standard LVPECL(3.3V) signal to virtex-II pro device. But I know that Virtex-II Pro devices support only LVDS_25 and LVPECL_25. There is no problem with Spartan-IIE or Virtex-II device because they have a LVPECL_33 I/O. I want to know how I connect between standard LVPECL(...


Virtex-4 RocketIO and G.709 OTU-2

Started by in comp.arch.fpga15 years ago 14 replies

Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is...

Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is 10.709. Should Virtex-4 be definitively excluded or are there some tricks to achieve that challenge? Cheers Mehdi


3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4

Started by Dale in comp.arch.fpga14 years ago 1 reply

I want to drive a LVPECL_25 input on a bank with VCCO=2.5V with a 3.3V LVPECL signal. Xilinx has a nice app note on doing this with a Virtex ii...

I want to drive a LVPECL_25 input on a bank with VCCO=2.5V with a 3.3V LVPECL signal. Xilinx has a nice app note on doing this with a Virtex ii and a Spartan 3, but I can't find anything concrete about doing it on a Virtex-4. Would you agree that it's safe to implement the same solution on a Virtex-4? Here's the app note: http://www.xilinx.com/bvdocs/appnotes/xapp696.pdf See page 4. ...


Virtex 4 and reconfigurable computer

Started by in comp.arch.fpga16 years ago 2 replies

Hi! I would like to know if the Xilinx Virtex 4 offer the possibility of partially reconfigure bitstreams directly (as in the virtex II...

Hi! I would like to know if the Xilinx Virtex 4 offer the possibility of partially reconfigure bitstreams directly (as in the virtex II using the jbits library). If yes ... what are the hardware (requirement for the fpga board) and software (are the libraries similar to jbits?) requirements ? Thanks in advance. Cheers !


Avnet Xilinx Virtex-II Pro Development Kit

Started by Mindroad in comp.arch.fpga16 years ago

board : Avnet Xilinx Virtex-II Development Kit fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ... problem : avnet includes a ucf file...

board : Avnet Xilinx Virtex-II Development Kit fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ... problem : avnet includes a ucf file for this FPGA stating the physical pinning for an externally attached ddr sdram of 128MB With Base System Builder Wizzard in EDK/XPS I create a design for the virtex II Pro 7, they haven't got one for the 20 ... Since the 7 and the 20 FPGAs have the


Issues with a batch of Virtex-II chips

Started by IgI in comp.arch.fpga16 years ago 9 replies

Hi! I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we have been selling for over 3 years. Recently we got "new" batch of...

Hi! I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we have been selling for over 3 years. Recently we got "new" batch of Virtex-II chips and problems started to arise. So far I have isolated PCBs with three different batch of Virtex-II chips: Batch A: XC2V1000 FF896AFT0301 F1247582A 4C Philippines Batch B: XC2V1000 FF896AGT0409 D2169507A 4C Taiwan Batc...


Help (Virtex 155 and 220 compatibility) !

Started by Kazu in comp.arch.fpga11 years ago 1 reply

I had a board which mounted Virtex 155. I've changed the FPGA to Virtex 220. The support engineer of Xilinx sales company said both FPGAs...

I had a board which mounted Virtex 155. I've changed the FPGA to Virtex 220. The support engineer of Xilinx sales company said both FPGAs were compatible and there was no problem. But all 4 board I changed FPGA don't work at all. Even JTAG interface doesn't work. Are they actually compatible? Or do we need to modify the board to mount Virtex 220? Kazu


Multiple GTPs used in a Virtex 5

Started by Roger in comp.arch.fpga12 years ago 2 replies

I want to use 14 GTPs on a Virtex 5 each running a separate Aurora interface. The Aurora code from Coregen produces a clock_module process...

I want to use 14 GTPs on a Virtex 5 each running a separate Aurora interface. The Aurora code from Coregen produces a clock_module process amongst all the others which contains a DCM. Previous experience of Virtex II Pro implementations allowed 1 clock module to be used with multiple Auroras. The Virtex 5 clock module is different in that it takes its clock input from the GTP Dual PLL t...


Difference among Virtex Families, FPGA Books

Started by rk in comp.arch.fpga11 years ago 10 replies

Hi Folks I have recently become very interested in FPGA and DSP. Could somebody suggest to me a newbee started book and also a related...

Hi Folks I have recently become very interested in FPGA and DSP. Could somebody suggest to me a newbee started book and also a related experimental board. I would also like to know the differences between the different Virtex families like Virtex 2, 4, 5 etc. Regards RK


Xilinx Virtex-4 Clock Multiplexer Inputs

Started by Elmo Fuchs in comp.arch.fpga14 years ago 4 replies

Hi all, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the possibility to...

Hi all, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the possibility to route various clock signals to several domains on the FPGA and select them locally by specific clock multiplexer inputs. Because of the restricted amount of available pins on the device I selected (Virtex-4 FX40 with 352 user I/Os) I would like to us...


BRAM for virtex-4

Started by bach...@gmail.com in comp.arch.fpga15 years ago 2 replies

Hi all, i am using the following code for BRAMs and i copied these instantiations from virtex-4 libraray.But still i am getting an...

Hi all, i am using the following code for BRAMs and i copied these instantiations from virtex-4 libraray.But still i am getting an error message when i am trying to implment it using xilinx ise7.1 on virtex-4 fpga.It is giving an error message like .ngd build failed.Can anyone help me in solving this problem. thanks, Regards Ramakrishna ---------------------------------------------...


General Question - Which FPGAs can support partial run-tim reconfiguration?

Started by nickel in comp.arch.fpga16 years ago 1 reply

Hi, As far as I know, only Xilinx (XC6200, Virtex, Virtex-E, Virtex II, Virtex 4) and Atmel (FPSLIC - AT94Kxx)support partial...

Hi, As far as I know, only Xilinx (XC6200, Virtex, Virtex-E, Virtex II, Virtex 4) and Atmel (FPSLIC - AT94Kxx)support partial run-time (dynamic) reconfiguration. Is there any other FPGA vendor being able to support partial run-time reconfiguration? What are they and what are the families? Thanks Regards Nickel


Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)

Started by Bruce in comp.arch.fpga17 years ago 2 replies

Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant...

Hello, at present I am working on an Infiniband implementation on a Virtex-II Pro. As far as I know the build-in RocketIOs are fully compliant to the Infiniband standard (beacon and variant CRC excluded). There are two types of CRC, the invariant and the variant type. Although the RocketIOs are able to calculate at least one type, i.e. the invariant CRC, you cannot make use of it in this par...


Virtex-4 availability?

Started by Anonymous in comp.arch.fpga17 years ago 1 reply

Now that the Virtex-4 has been announced: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 The obvious question is...

Now that the Virtex-4 has been announced: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 The obvious question is when and how much? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?


How to simulate Virtex-4 PPC, MAC, etc. ?

Started by acet...@gmail.com in comp.arch.fpga15 years ago 1 reply

Hello! Having finished a board design with a Virtex-4FX and with promising leads on the silicon, I sat down to begin my HDL coding... when I...

Hello! Having finished a board design with a Virtex-4FX and with promising leads on the silicon, I sat down to begin my HDL coding... when I discovered that the simulation models for the Virtex-4 PPC and MAC components are only available in encrypted form. After poking around a bit on the net and usenet, it seems that only the really high-end simulators can support these encrypted models. Has...