virtex-5 sysmon, really nice to monitor supply and temp

Started by Antti in comp.arch.fpga14 years ago 2 replies

Hi the sysmon is really available in ALL Virtex-5 devices below is voltage and temperature monitoring log screenshot...

Hi the sysmon is really available in ALL Virtex-5 devices below is voltage and temperature monitoring log screenshot from Chipscope http://www.xilant.com/downloads/cs82_sysmon.jpg the temperature drops seen in the log are my finger pressed to the top of the Virtex-5 package Antti


Virtex 7?

Started by step...@gmail.com in comp.arch.fpga11 years ago 3 replies

The CTO of Xilinx, during his keynote this morning at the Reconfigurable Architectures Workshop in Atlanta, made mention of the recent...

The CTO of Xilinx, during his keynote this morning at the Reconfigurable Architectures Workshop in Atlanta, made mention of the recent announcement of the Virtex 7 architecture. My colleagues and I assumed that either the announcement was very recent or not very well publicized as none of us had heard anything official regarding Virtex 7. A subsequent web search returned little except for a ...


Virtex Benchmarks

Started by PanJuHwa in comp.arch.fpga17 years ago

Hi, I'm currently working on an honours thesis involving configuration compression for Virtex FPGAs. I need to collect benchmarks in...

Hi, I'm currently working on an honours thesis involving configuration compression for Virtex FPGAs. I need to collect benchmarks in my analysis of the algorithms that I've implemented, for any Virtex devices, preferably with utilization > 70%. If you do not mind providing any bitstreams you have at hand for my research, please reply to this post or send them to me at panjuhwa_fpga@yahoo


Xilinx Memory Interface Generator

Started by Sean Durkin in comp.arch.fpga16 years ago

Hi *, I noticed that now the Xilinx Memory Interface Generator is available from http://www.xilinx.com/memory . This should be very...

Hi *, I noticed that now the Xilinx Memory Interface Generator is available from http://www.xilinx.com/memory . This should be very useful... On the page it says "Generate your Virtex-4, Virtex-II Pro and Spartan-3 memory interface", but in fact the tool you can download there only supports Virtex-4. Will Virtex-II Pro be supported in the near future or will MIG concentrate purely...


Routing Information of Xilinx's Virtex-II FPGA

Started by mano...@gmail.com in comp.arch.fpga15 years ago

Hi All, I am seeking for following information regarding Virtex-II FPGA: 1. Is it possible to know exact delay information of each type...

Hi All, I am seeking for following information regarding Virtex-II FPGA: 1. Is it possible to know exact delay information of each type of segment (signle line, double, hex lines etc.) present in Virtex-II? 2. Is it possible to now exact delay information of Programmable Interconnect Point(PIP) present between any two segments in Virtex-II? I tried to get above information from D...


SATA and RocketIO

Started by sg in comp.arch.fpga16 years ago 5 replies

Has anyone had any sucess in using RocketIO from Virtez 2 or Virtex 4 for Serial ATA applications? From the information collected on...

Has anyone had any sucess in using RocketIO from Virtez 2 or Virtex 4 for Serial ATA applications? From the information collected on various news groups and web sites, my understanding is SATA OOB cannot be done using RocketIO in Virtex 2s. Did any one try Virtex 4s? What is the comment from FPGA gurus out there? - sg


3.3V tolerant Virtex-4 JTAG Configuration

Started by Dale in comp.arch.fpga14 years ago 2 replies

Hello, I've been looking through Xilinx's website for quite some time now for information on using 3.3V to configure a Virtex-4 through the...

Hello, I've been looking through Xilinx's website for quite some time now for information on using 3.3V to configure a Virtex-4 through the JTAG interface. Is there anything equivalent to the link below for the Virtex 4? That's a very good document for the Spartan 3 and I'm hoping to find something similar for the V4. http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getP...


Evaluation Board for Xilinx Virtex

Started by in comp.arch.fpga16 years ago 2 replies

How to find a Evaluation board for Xilinx Virtex II Hallo, please can anybody help me? I want to program a Virtex II or Virtex Pro FPGA Chip....

How to find a Evaluation board for Xilinx Virtex II Hallo, please can anybody help me? I want to program a Virtex II or Virtex Pro FPGA Chip. Anybody knows an evaluation board to program this chips? I want to make a fast analogue digital converter and I want to make a performance check. Fist I wand to create a program with mathlab and than by hand with VHDL. Please can somebody tell m...


Issues with Synplify Pro 7.7 synthesis

Started by Harish Vutukuru in comp.arch.fpga16 years ago 2 replies

Hello All, I am a graduate student in Computer Engineering an am developing some small VHDL modules targeted to Xilinx Virtex devices. While I...

Hello All, I am a graduate student in Computer Engineering an am developing some small VHDL modules targeted to Xilinx Virtex devices. While I was trying to synthesize some of those designs using synpliciy I got the following error." Invalid LUT instantiation. Have you included the virtex.v(hd) file, and an INIT value @E:Internal Error". I tried adding virtex.vhd from synplicity installati...


Location of Virtex4 ASCII pinout tables

Started by Anonymous in comp.arch.fpga15 years ago 4 replies

I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under "Products") This brings up the...

I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under "Products") This brings up the URL http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/index.htm At this URL, on the right, under "Related Information", there is a link named "Virtex-4 package files" The actual URL this link points to is http://www.xilinx.com/products/virtex4/virtex-4-pkgs.htm ...


Virtex-II Pro CRC Test Data

Started by David in comp.arch.fpga14 years ago 1 reply

I've written a program to calculate the CRC of Virtex-II Pro bit stream and I'm having trouble validating my results. Testing it against...

I've written a program to calculate the CRC of Virtex-II Pro bit stream and I'm having trouble validating my results. Testing it against an existing bit stream, I do not get the right CRC result but I'm not sure if it's my calculations or how I am choosing which data is incorporate into the CRC. I've based my code on the Virtex Series Configuration Architecture Users Guide (XAPP151) and the...


Virtex-II Speed grade -6 exist?

Started by Anonymous in comp.arch.fpga17 years ago 3 replies

Hi guys, I was informed (don't remember who told me/ or where it came from) that the Virtex-II is also available in speed -6, is that true? ...

Hi guys, I was informed (don't remember who told me/ or where it came from) that the Virtex-II is also available in speed -6, is that true? For my understand the Virtex-II family just has -4 and -5 speed grade. Pls clarify me.


Virtex-4 BiDirectional Ports

Started by Brad Smallridge in comp.arch.fpga15 years ago 1 reply

How does one properly synthesize and simulate a bidirectional port on the Virtex-4 using ISE 7.1i. I drafted code from an earlier Spartan 3...

How does one properly synthesize and simulate a bidirectional port on the Virtex-4 using ISE 7.1i. I drafted code from an earlier Spartan 3 design, which synthesized nicely. On the Virtex-4, the T signals is not registered although the block diagram indicates that it could be. Also, the ISE simulator does not show any output values on the inout ports. Thanks, Brad Smallridge s...


Virtex-II Pro ML-300 Evaluation Platform

Started by Rudy Hartmann in comp.arch.fpga17 years ago 1 reply

Virtex-II pro ML-300 Evaluation Platform For Sale Cheap! I have one piece of a brand new Xilinx Virtex-II pro ML-300 Evaluation Platform for...

Virtex-II pro ML-300 Evaluation Platform For Sale Cheap! I have one piece of a brand new Xilinx Virtex-II pro ML-300 Evaluation Platform for sale. It is brand new and in the original factory box. Everything that came shrink wrapped is still sealed. It's never been opened or used. The part number is DO-V2P-ML300-USA. The Virtex-II ProT ML300 Evaluation Platform allows designers to investiga...


Virtex 4 and 5

Started by randyddr in comp.arch.fpga12 years ago 1 reply

We're interested in buying any overstock or excess Virtex-4 , Virtex-5 or Spartan inventory you may have. Please email me...

We're interested in buying any overstock or excess Virtex-4 , Virtex-5 or Spartan inventory you may have. Please email me at randyh@advancedmp.com . I know inventory on these can be costly so hopefully we can help. We can handle large volume purchases. thanks, Randy randyh@advancedmp.com


Virtex 5 PCB Designers Guide: required capacitors

Started by Anonymous in comp.arch.fpga13 years ago 1 reply

Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provided by Avnet ) as model,...

Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provided by Avnet ) as model, and the Xilinx App Note "Virtex 5 PCB User guide 203". My problem is about the capacitors required by the FPGA. In the pcb user guide, there is a section wich details the list of required capacitors / slices. Capacitors used are 330uF, 2.2uF, and ...


Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O

Started by Vivek Menon in comp.arch.fpga15 years ago 3 replies

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation...

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation board. After I program the FPGA and the Rocket I/O, I need to detach the board/mini-module. Please let me know if you are aware of such mini-modules. Thanks, Vivek


Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O

Started by Vivek Menon in comp.arch.fpga15 years ago

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation...

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation board. After I program the FPGA and the Rocket I/O, I need to detach the board/mini-module. Please let me know if you are aware of such mini-modules. Thanks, Vivek


Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O

Started by Vivek Menon in comp.arch.fpga15 years ago

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation...

Hi, I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series FPGA with rocket I?O capability. I do not want a huge evaluation board. After I program the FPGA and the Rocket I/O, I need to detach the board/mini-module. Please let me know if you are aware of such mini-modules. Thanks, Vivek


User Core to PLB Bus example for Virtex 2P in EDK.

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Does anyone has an example of a user IP core hooked up to the PLB bus for a Virtex 2P in EDK? I am wondering how I can get my core to be...

Does anyone has an example of a user IP core hooked up to the PLB bus for a Virtex 2P in EDK? I am wondering how I can get my core to be connected to the PLB bus in the Virtex 2P anmd controlled it viua Software, I am using Xilinx EDK. Thanks NR