Virtex-4 SELECT MAP configuration

Started by Pasacco in comp.arch.fpga13 years ago 1 reply

Hi Let me ask two questions --: According to Virtex-4 configuaration guide (http://www.xilinx.com/bvdocs/userguides/ug071.pdf), ICAP...

Hi Let me ask two questions --: According to Virtex-4 configuaration guide (http://www.xilinx.com/bvdocs/userguides/ug071.pdf), ICAP interface is either 8-bit or 32-bit, with up to 60MHz CCLK. Most of diagrams and explanations are based on 8-bit interface. I also saw one document, in which latest VIrtex-4 ICAP provides 32-bit interface with 100 MHz. I wonder if 32-bit interface ope...


How do I make use of local-clocks in a Virtex-2 FPGA?

Started by Kelv...@ SG in comp.arch.fpga17 years ago 1 reply

Hi, there: I saw this statement in Virtex-2 datasheet, how do I make use of these local clocks? Is there any documents on these local...

Hi, there: I saw this statement in Virtex-2 datasheet, how do I make use of these local clocks? Is there any documents on these local clocks? Best Regards, Kelvin Local Clocking In addition to global clocks, there are local clock resources in the Virtex-II devices. There are more than 72 local clocks in the Virtex-II family. These resources can be used for many different applic...


Virtex-4 ISERDES and ADS527X ADCs

Started by Sean Durkin in comp.arch.fpga15 years ago 25 replies

Hi *, I'm having a litte problem trying to understand some things regarding the ISERDES in Virtex-4-IOs. Here's what I want to do: We...

Hi *, I'm having a litte problem trying to understand some things regarding the ISERDES in Virtex-4-IOs. Here's what I want to do: We use a lot of ADS527X-ADCs from TI. Those parts output 12bit/sample via LVDS-DDR-links running at up to 480Mbit/s. Up to now, using Virtex-2 Pro, getting this into the FPGA is a little tricky (see xapp774). In short, the current way is to feed the serial...


Sythesis software for Virtex-4

Started by Waage in comp.arch.fpga15 years ago 9 replies

Hi, I are looking to purchase some FPGA software in the very near term for a project utilizing Xilinix's Virtex-4 device. I are relatively...

Hi, I are looking to purchase some FPGA software in the very near term for a project utilizing Xilinix's Virtex-4 device. I are relatively new to FPGA design and would appreciate any comments from those who have experience with Virtex-4 regarding FPGA synthesis software options. I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions. Are there any recommendations for or ...


Help with Virtex II and 5v TTL

Started by Jim in comp.arch.fpga16 years ago 4 replies

Help, I've been trying to find a definitive answer to this question. Can I connect Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL)...

Help, I've been trying to find a definitive answer to this question. Can I connect Virtex II pins configured as pure outputs (LVCMOS33 or LVTTL) directly to 5v LSTTL, ACT, or FCT INPUTS without any resistors and not risk any damage ? I've used the quickswitch design from the appnotes for my bidirectional pins, and 175 ohm series resistors for 5v TTL inputs to the Virtex II, but I tied th...


Virtex-4 RocketIO

Started by Peter Mendham in comp.arch.fpga15 years ago 2 replies

Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for development involving...

Dear all, I'm in the early stages of designing a board with a Virtex-4 FX on it which we are planning to use for development involving RocketIO. The other guys on the team have stated that it would be "really useful" to have the clock for the RocketIO fed from a programmable oscillator. We have a Virtex-II FX development board that has a similar arrangement, using a ICS8442 low jitt...


Virtex-4 FX transceiver jitter

Started by Allan Herriman in comp.arch.fpga17 years ago 1 reply

Hi, Does anyone know if the (just announced) Virtex-4 FX transceivers will have jitter characteristics suituable for SONET work at...

Hi, Does anyone know if the (just announced) Virtex-4 FX transceivers will have jitter characteristics suituable for SONET work at 10Gb/s? The current (V2PX) transceivers aren't able to meet the jitter specs, forcing the use of external SERDES devices. There's not much real information on the web page yet. http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-4 TIA, All...


Xilinx FPGA Die Size

Started by Ryan Fong in comp.arch.fpga17 years ago 1 reply

Fellow comp.arch.fpga users, I'm trying to obtain information die sizes for various Xilinx FPGAs in the Virtex, Virtex-II Pro, Virtex-II, and...

Fellow comp.arch.fpga users, I'm trying to obtain information die sizes for various Xilinx FPGAs in the Virtex, Virtex-II Pro, Virtex-II, and Spartan-III families. I am using this information in my Master's thesis to approximate the physical lengths of long wires, and how they have been scaling with delay. Any pointers will help. Thanks. -Ryan


TI DSP + Virtex-5 using EMIF interface

Started by techG in comp.arch.fpga13 years ago 2 replies

Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and...

Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and an hardware parallel solution can help to satisfy time constraints. Finally I decided for a mixed SW and HW that consists in a TI DSP and a Virtex-5 connected togheter on EMIF. Initially I choosed a Virtex-5SX, because it has a large number of DSP ...


minimum software for virtex II pro

Started by myren in comp.arch.fpga17 years ago 1 reply

what is the minimum software required to take advantage of a virtex II pro (in terms of cost)? just a poor college student trying to learn...

what is the minimum software required to take advantage of a virtex II pro (in terms of cost)? just a poor college student trying to learn fpga's. Virtex II pro is obviously a bit excessive, but my main reason for learning fpga's is to begin to do high bandwidth data shuffling. the rocketio seems well suited to that, and i'm hoping with EDK i might actually be able to implement giga...


clock multiplexor device

Started by Elmo Fuchs in comp.arch.fpga14 years ago 2 replies

Hi, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the possibility to route...

Hi, I'm currently developing a PCB featuring a Xilinx Virtex-4 device. Unlinke the Virtex-II series they now offer the possibility to route various clock signals to several domains on the FPGA and select them locally by specific clock multiplexer inputs. Because of the restricted amount of available pins on the device I selected (Virtex-4 FX40 with 352 user I/Os) I would like to use just o...


Am I blind or? (Virtex-4 issues)

Started by Antti in comp.arch.fpga14 years ago 6 replies

Hi, Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required to readback data from...

Hi, Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required to readback data from XCF devices, this approuch is described in Xilinx Application note XAPP482. Until today I did live in believe that this was the reason why startup primitive was modified in Virtex-4, but today I was about to check the pinout for XCF data read able de...


Virtex-4 FX devices availablity issues

Started by Sean Durkin in comp.arch.fpga16 years ago 1 reply

Hi, has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX bigger than the FX12? And I'm talking about seeing it in real...

Hi, has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX bigger than the FX12? And I'm talking about seeing it in real life, holding it in your hand, putting it on your boards, not just seeing a Xilinx-manufactured, unpowered eval-board at some trade fair... Originally, we wanted to use a Virtex-4 FX20 in our latest design. Cool new part for a cool new prototype, we thought...


Aurora cores

Started by Roger in comp.arch.fpga12 years ago

In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is...

In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is the best to use? Presumably the "Virtex 5" version, is this right? What's the difference anyway? In my project several dual tiles will be used, clocked via the GTP Dedicated Clock Routing from 2 sources. How is the clock routing set-up? Once set it...


can anyone give me a reference price of the following Xilinx boards?

Started by wicky in comp.arch.fpga14 years ago 4 replies

I can't check any price infomation about the following boards in xilinx website: 1) ML521/3/5 ---- Virtex-5 GTP characterization board. 2)...

I can't check any price infomation about the following boards in xilinx website: 1) ML521/3/5 ---- Virtex-5 GTP characterization board. 2) ML550 ---- Virtex-5 networking development board. Btw: what about Virtex-5 VSK (Video Starter Kit), I hear that it will support PCI-e. Thanks a lot. Best Regards, Wicky


Simple Aurora Coregen queries

Started by Roger in comp.arch.fpga12 years ago

In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is...

In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is the best to use? Presumably the "Virtex 5" version, is this right? What's the difference anyway? In my project several dual tiles will be used, clocked via the GTP Dedicated Clock Routing from 2 sources. How is the clock routing set-up? Once set...


xilinx MGT compatibility?

Started by Tullio Grassi in comp.arch.fpga16 years ago 1 reply

Hi, can the MGT of Virtex-4FX talk to the MGT of Virtex-2Pro (XC2VPX) ? Any experience or problems ? Tullio

Hi, can the MGT of Virtex-4FX talk to the MGT of Virtex-2Pro (XC2VPX) ? Any experience or problems ? Tullio


Need help with the I/O Standard

Started by kashif in comp.arch.fpga12 years ago 1 reply

HI I have a PCB which has a TI IC for the PHY layer controller and I want to connect the PCB with the Virtex II xc2v8000 FPGA. But I need...

HI I have a PCB which has a TI IC for the PHY layer controller and I want to connect the PCB with the Virtex II xc2v8000 FPGA. But I need information about the I/O Standard of the Virtex II. The output ports on the PCB are Bidirectional and they accept 4.4 volts I/O Standard but I checked the datasheet of the virtex II Chip and I found that the maximum volts for the output and input are 3.3 Volts...


Virtex and Spartan

Started by Bhadri in comp.arch.fpga17 years ago 3 replies

Hello can anyone say me what is the difference between virtex and spartan fgpa chips. It is just the number of gates in them, voltage levels or...

Hello can anyone say me what is the difference between virtex and spartan fgpa chips. It is just the number of gates in them, voltage levels or anything more than that. I have used spartan chips.i configured the chip with different vhdl files again and again on the same chip.But somebody said it is not possible in the xcv1000 virtex chips.(dynamically reconfigurable).Is it true.Then,y are ...


VIRTEX v Spartan 3

Started by chuk in comp.arch.fpga17 years ago 24 replies

Out of interest, would anyone happen to know what is the difference in performance between a Virtex fpga (not vitex 2) and its...

Out of interest, would anyone happen to know what is the difference in performance between a Virtex fpga (not vitex 2) and its equivalent Spartan3??? Thanks C