JBits and Spartan

Started by alonzo in comp.arch.fpga16 years ago 5 replies

Hello, Does somebody know if the last version of JBits (3.0) will work with spartans family? I know JBits 3.0 supports Virtex II, and an older...

Hello, Does somebody know if the last version of JBits (3.0) will work with spartans family? I know JBits 3.0 supports Virtex II, and an older version supported Virtex... but .. Spartan is kind of a Virtex.. so .. have anyone try this before? Thanks, Alonzo.


3/2 with virtex 300

Started by HB in comp.arch.fpga15 years ago 11 replies

Hi, I use a Virtex XCV300 I would like to do : a multi *3 and a div /2 with a clk = 32 MHz. (I would like to obtain a freq = 48 MHz) Can...

Hi, I use a Virtex XCV300 I would like to do : a multi *3 and a div /2 with a clk = 32 MHz. (I would like to obtain a freq = 48 MHz) Can you help me !!. Thanks and regards, Benoit.


Problems with a Virtex-II Engineering Sample

Started by Jonas Floden in comp.arch.fpga17 years ago 10 replies

Hello all, We are currently doing a project where we would like to evaluate the advantages of the PPC405 hard processor core in the Virtex-II...

Hello all, We are currently doing a project where we would like to evaluate the advantages of the PPC405 hard processor core in the Virtex-II Pro FPGA compared to the Microblaze soft core. We've got the Microblaze up and running but we are struggling to get the PPC to execute any code. The chip is an Engineering Sample: Virtex-II Pro XC2VP7 FF672ALB0237 D127316A 6C-ES The progra...


Xilinx Virtex 4 question

Started by Andreas Schallenberg in comp.arch.fpga16 years ago 14 replies

Hello! From the Virtex 4 documentation (Configuration Guide, Users Guide) I learned that this family can be configured during runtime in the...

Hello! From the Virtex 4 documentation (Configuration Guide, Users Guide) I learned that this family can be configured during runtime in the granularity of single frames. The frames which have a fixed size for all members of this family. Additionally the documents state that there is a tiled placement of those frames. For Virtex II the frames started at the topmost CLB and ended at th...


Partial Reconfiguration of Virtex-5: ISE and EAPR?

Started by kyprianos in comp.arch.fpga13 years ago 7 replies

Hi all, Does anyone know whether Virtex-5 devices are supported by the Partial Reconfiguration design flow. I understand that PlanAhead...

Hi all, Does anyone know whether Virtex-5 devices are supported by the Partial Reconfiguration design flow. I understand that PlanAhead supports it but which versions of the ISE and the EAPR support partial reconfiguration for Virtex-5? Thanx kyprianos


Xilinx Virtex 4

Started by Andreas Sch. in comp.arch.fpga17 years ago 5 replies

Hi, does anybody know if the Virtex 4 family still has some dynamic partial reconfiguration capability? I haven't found this information on...

Hi, does anybody know if the Virtex 4 family still has some dynamic partial reconfiguration capability? I haven't found this information on their website :( Andreas


How do I instantiate GT11CLK_MGT?

Started by MM in comp.arch.fpga16 years ago 1 reply

The Virtex-4 lib manual suggests that the Architecture Wizard should be used, however I can't see how... The Virtex-4 RocketIO Guide doesn't...

The Virtex-4 lib manual suggests that the Architecture Wizard should be used, however I can't see how... The Virtex-4 RocketIO Guide doesn't seem to have this information either... Thanks, /Mikhail


Looking for Virtex-6 PCIe development board

Started by Poojan Wagh in comp.arch.fpga12 years ago 3 replies

Does anyone know of anyone that can shp a Virtex-6 PCIe development board (within about 4 weeks)? Xilinx still doesn't seem to have their...

Does anyone know of anyone that can shp a Virtex-6 PCIe development board (within about 4 weeks)? Xilinx still doesn't seem to have their evaluation/development kits for Virtex-6 ready to ship.


vertex-II configuration architecture

Started by sudarshan banerjee in comp.arch.fpga17 years ago 1 reply

I have a question about Virtex-II configuration architecture. Any help/pointers would be greatly appreciated. Thanks, Sudarshan ...

I have a question about Virtex-II configuration architecture. Any help/pointers would be greatly appreciated. Thanks, Sudarshan problem: according to XAPP 151 (vertex config architecture user's guide), each CLB column in Virtex has 48 frames So, XC2V2000 (56 rows 48 columns), should have at least 48 * 48 = 2244 frames however, Virtex-II platform us


Can Xilinx IST automatically detect non-compatible library?

Started by Weng Tianxiang in comp.arch.fpga12 years ago 2 replies

Hi, When I was generating my code, I didn't know what exact Xilinx chip may be used so that I selected Virtex V chip as my target one...

Hi, When I was generating my code, I didn't know what exact Xilinx chip may be used so that I selected Virtex V chip as my target one time. During the development, I might have tried to generate libraries with Virtex II chips because I have many Virtex II libraries ready to use. It led to the situation that I really don't know which library belongs to which chip. For simulations, it doesn't ...


memories for virtex-4 and Spartan-3E

Started by bach...@gmail.com in comp.arch.fpga15 years ago 1 reply

Hi all, i am looking for VHDL instantiation of BRAMs and LUT memories .i copied those instantiations from libraries of Virtex-4 and Spartan-3E....

Hi all, i am looking for VHDL instantiation of BRAMs and LUT memories .i copied those instantiations from libraries of Virtex-4 and Spartan-3E. But still they are not getting synthesized and implemented.Can someone suggest me where to look for these instantiations or can some one send me codes for BRAMs and LUT memories in Virtex-4.i need them urgently. thanks Regards Ramakrishna ...


Virtex 13?

Started by BobW in comp.arch.fpga13 years ago 4 replies

I was just eating some spicy food for lunch and I started wondering whether Xilinx would eventually come out with a Virtex 13 family or would...

I was just eating some spicy food for lunch and I started wondering whether Xilinx would eventually come out with a Virtex 13 family or would they skip it due to superstitious reasons? Thanks. Bob


gate capacity between old Virtex-II and newer Virtex-4

Started by stevem in comp.arch.fpga12 years ago 3 replies

I used a Virtex-II XC2V1000 some time ago. The datasheet says the capacity is ~1M system gates with 5,120 slices. Now, I am looking at a...

I used a Virtex-II XC2V1000 some time ago. The datasheet says the capacity is ~1M system gates with 5,120 slices. Now, I am looking at a Virtex-4 XC4VLX25. The datasheet says this has 10,752 slices but no longer gives the equivalent "system gates" capacity. Question: how do I compare the capcity of XC4VLX25 to the XC2V1000 ? is the capacity of XC4VLX25 =2X the capaci...


Virtex-II : Architecture

Started by Cyrille Lambert in comp.arch.fpga16 years ago 2 replies

Hi everybody, I cannot find any paper or application note on the Virtex-II architecture. Do you know where could I find it? In order to know...

Hi everybody, I cannot find any paper or application note on the Virtex-II architecture. Do you know where could I find it? In order to know more about the bitstream in the spirit of the xapp151 for example. By the way, if this application note reflects the architecture of the Virtex-II tell me please, I am a bit lost. Thanks by advance, /Cyrille Lambert


VIRTEX-6 FXT announced soon?

Started by Antti in comp.arch.fpga12 years ago 4 replies

AR32929 " Description Keywords: Virtex-6, issues, LXT, SXT, FXT, CXT " i would assume 6FXT has some hard processor core? or is it...

AR32929 " Description Keywords: Virtex-6, issues, LXT, SXT, FXT, CXT " i would assume 6FXT has some hard processor core? or is it all typos in Xilinx web? Antti


Virtex-5 are available from distribution

Started by Peter Alfke in comp.arch.fpga14 years ago

As I mentioned before, Virtex-5 devices are plentifully available at Xilinx, and now also from Avnet and NuHorizon. The outcry in this newsgroup...

As I mentioned before, Virtex-5 devices are plentifully available at Xilinx, and now also from Avnet and NuHorizon. The outcry in this newsgroup helped to speed up the process ! The easiest way is to go to www.xilinx.com, click on the Xilinx store listing in the lower left hand corner, then click on Virtex-5 in the upper right hand corner, and admire the long list of available parts. Then cl...


Why the second flip-flop in Virtex-6?

Started by Nathan Bialke in comp.arch.fpga12 years ago 33 replies

Hello, In case anyone hasn't already seen, Xilinx has some preliminary information about Virtex-6 and Spartan-6 online here...

Hello, In case anyone hasn't already seen, Xilinx has some preliminary information about Virtex-6 and Spartan-6 online here - http://www.xilinx.com/products/v6s6.htm . I do have a question about Virtex-6 and it's one LUT6/two flip-flop architecture. I'm struggling to think of why a user would have any use for that second flip-flop. It seems to me that the second flip-flop only has use w...


Are modules that are not floorplanned still functional?

Started by Jiang in comp.arch.fpga17 years ago 2 replies

Hello, FPGA friends, I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with an FF1152 board. My ISE is version 5.2.03i. In...

Hello, FPGA friends, I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with an FF1152 board. My ISE is version 5.2.03i. In the beginning I could do a trivial bypassing using Virtex 2000E with a BG560 board: input clk; output out_clk; wire out_clk; out_clk=clk; But on my Virtex-II 6000 it didn't work. It's fine since that I could try FDDRRSE to accomplish the sa...


System Monitor in Virtex-4

Started by Lars in comp.arch.fpga15 years ago 5 replies

I stumbled upon the System Monitor feature in the Virtex-4 handbook while looking for the DXN/DXP pins from Virtex-II for...

I stumbled upon the System Monitor feature in the Virtex-4 handbook while looking for the DXN/DXP pins from Virtex-II for temperature supervision. Perfect, just what we need! Both temperature and power supply supervision, without the hazzle of external SMBus measuring devices, voltage comparators and the like. Only trouble is (gee wizz..) the feature is marked as "NOT supported" in Xilinx ...


Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF

Started by Anonymous in comp.arch.fpga14 years ago 5 replies

Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Module...

Hello, I am trying to get the Virtex-4 Ethernet MAC Wrapper IP Core up and running on my Avnet Virtex-4 FX12 Mini Module (http://tinyurl.com/ yqc6ah), and I am having all sorts of problems. One of the main problems right now seems to be my understanding of the UCF file and what to edit or not to edit, since the rest of the design should be already set up fine from what I have read in the u...