Using DCM-Virtex-II Pro

Started by junaidabidi in comp.arch.fpga15 years ago 2 replies

Hi, I using Xilinx System Generator tool and need to use DCM for Virtex-II Pro board. But after searching on internet I could not find...

Hi, I using Xilinx System Generator tool and need to use DCM for Virtex-II Pro board. But after searching on internet I could not find any relevant material. Any kind of help will be highly appreciated. Junaid


Xilinx Virtex 4

Started by jon in comp.arch.fpga13 years ago 1 reply

I need help with immediate delivery of two Virtex 4 FPGA's. The part numbers are XC4VLX80-11FFG1148C (50pcs) and XC4VLX25-11FFG668C (25pcs)....

I need help with immediate delivery of two Virtex 4 FPGA's. The part numbers are XC4VLX80-11FFG1148C (50pcs) and XC4VLX25-11FFG668C (25pcs). Anything that you can do is appreciated. Regards, Jon E. Hansen (949)864-7745


32x32 -> 64 multiplier in virtex-5

Started by Muzaffer Kal in comp.arch.fpga12 years ago 6 replies

Hi, I'm porting an ASIC design to virtex-5. In the design there is a 32x32-> 64 bit signed multiplier and I can't seem to do any better...

Hi, I'm porting an ASIC design to virtex-5. In the design there is a 32x32-> 64 bit signed multiplier and I can't seem to do any better than synthesis at this point (tried two different synthesis tools which give the same results also). What would be the fastest way to do a 32x32 multiplier in Virtex-5? I'm trying to get it to run at 125 MHz on a xc5vlx50-1. Area is no problem and I'm current


Statix II vs. Virtex 4

Started by Tim Michaels in comp.arch.fpga17 years ago 11 replies

Although I have not posted yet to this group, I have an FPGA question. I am doing an evaluation of the Stratix II and the Virtex 4. ...

Although I have not posted yet to this group, I have an FPGA question. I am doing an evaluation of the Stratix II and the Virtex 4. Does anyone have any comparisons or experience of the features, performance, etc. of the two devices? I am trying to understand the tradeoffs of the two different platforms.


Problem with Virtex-4 IBIS model

Started by dudesinmexico in comp.arch.fpga13 years ago 7 replies

I am setting up a signal integrity simulation of a Virtex-4 DDR2 memory interface with Agilent's ADS. According to the readme file in the...

I am setting up a signal integrity simulation of a Virtex-4 DDR2 memory interface with Agilent's ADS. According to the readme file in the Virtex-4 IBIS distribution, on has to add a "a 50-65 ohm transmission line with 10-200ps of delay" to properly model package parasitics, so I have added a transmission line between the driver output and the PCB load. The IBIS model, however, already has a ...


Virtex-4 FX12 EMAC with ISE WebPack

Started by acet...@gmail.com in comp.arch.fpga15 years ago 3 replies

First, thank you xilinx for moving the functionality previously available in Base-X to the free WebPack. I was somewhat confused by...

First, thank you xilinx for moving the functionality previously available in Base-X to the free WebPack. I was somewhat confused by the literature on the website, but a call to support confirmed that the ISE 8.1 WebPack will support all Base-X devices, including the Virtex-4 FX12. However, no one I talked to could confirm if it was possible to use the Virtex-4 hard EMAC primitive without c...


Rosetta Results

Started by Austin Lesea in comp.arch.fpga16 years ago 9 replies

All, http://tinyurl.com/clzqh Details the latest readouts for actual single event upsets for Virtex 4, and Spartan 3. The improvements...

All, http://tinyurl.com/clzqh Details the latest readouts for actual single event upsets for Virtex 4, and Spartan 3. The improvements (6 times fewer upsets for Virtex 4, and 2.4 times fewer upsets for Spartan 3 as compared to Virtex II) shows our commitment to making this a non-issue for our customers. Make sure you demand from you ASIC/ASSP/FPGA vendor reports on their SEU su...


Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell?

Started by Weng Tianxiang in comp.arch.fpga12 years ago 9 replies

Hi, I don't like to print download version of many documents. The download prints are huge and not easy to keep them in order. So that I...

Hi, I don't like to print download version of many documents. The download prints are huge and not easy to keep them in order. So that I bought Virtex-4 FPGA Handbook for $10 years ago, and I want to buy Virtex-5 FPGA Handbook too, but cannot find the related information. I also want to buy Altera's Data Handbook. I will appreciate if anyone can pose the website for these books if th...


Virtex-5: small little things.

Started by Antti in comp.arch.fpga15 years ago 3 replies

Xilinx isnt advertizing 'small things' that are also coming as bonus with Virtex-5, I found one by accident while browsing the ML501 reference...

Xilinx isnt advertizing 'small things' that are also coming as bonus with Virtex-5, I found one by accident while browsing the ML501 reference designs and docu, namly * Virtex-5 has fully dedicated pins for the parallel flash so any NOR flash connected properly as configuration memory is also accessible by the dedicated pins for both read and writes. Those it is possible to use indirect no...


API on Virtex 4 FPGA or the email of Delon Levi wanted

Started by Anonymous in comp.arch.fpga15 years ago 2 replies

Hi all, I'm making research on Hardware Evolution and has bought a Development Board named DS-BD-V4LX25LC REVISION 2(VIRTEX-4 LC inside) of...

Hi all, I'm making research on Hardware Evolution and has bought a Development Board named DS-BD-V4LX25LC REVISION 2(VIRTEX-4 LC inside) of Memec Design. I learned that Delon Levi developed the API on Virtex 4 FPGA, and i need it urgently on the academic research(i declare that it would be use on academic research only). Would you please tell me where can I get a copy of the API or tell...


TAP controller state vs PROG pin

Started by Anonymous in comp.arch.fpga17 years ago 1 reply

I know that for Virtex, Virtex-E, and Spartan-II devices, TAP controller is held in reset state when PROG pin is low. This results that JTAG...

I know that for Virtex, Virtex-E, and Spartan-II devices, TAP controller is held in reset state when PROG pin is low. This results that JTAG chain cannot be used then. This was not the case for older devices (Spartan). Anybody knows how what's the situation in newer devices (I'm particularly curious about Virtex II )? Thanks. -- Robert


Virtex-5 and powerpc

Started by Anonymous in comp.arch.fpga14 years ago 6 replies

I cannot find any reference to powerPC cores in any of the Virtex-5 datasheets. The only reference to PowerPC in those documents is that PowerPC...

I cannot find any reference to powerPC cores in any of the Virtex-5 datasheets. The only reference to PowerPC in those documents is that PowerPC is a trademark of IBM. Does anyone know if Xilinx stopped including PowerPC cores in virtex-5 and why? Thanks


High Bandwidth Virtex II boards

Started by Steven Archibald in comp.arch.fpga18 years ago 2 replies

I'm trying to find a board consisting of a Virtex II or Virtex II Pro and a fair amount of on-board memory i.e. 256 or 512MB. The board has to...

I'm trying to find a board consisting of a Virtex II or Virtex II Pro and a fair amount of on-board memory i.e. 256 or 512MB. The board has to be capable of outputting the data read from memory through some kind of port at very high bandwidth - GBytes/s. It also has to be attached to either a PCI interface or preferably a VMEbus. Does anyone know of any single boards, or boards that could be ...


Looking for a decent FPGA board with multiple Xilinx Virtex 5 FPGAs

Started by maverick in comp.arch.fpga9 years ago 1 reply

Hi, I am looking for a decent PCIe (Gen1 & Gen2) based FPGA board with preferably 2 Xilinx Virtex 5 FPGAs on it. A 2GB DDR2 SODIMM and minimum...

Hi, I am looking for a decent PCIe (Gen1 & Gen2) based FPGA board with preferably 2 Xilinx Virtex 5 FPGAs on it. A 2GB DDR2 SODIMM and minimum 256 MB RAM is preferred. Other onboard periphals may include gigbit ethernet and a USB 2.0. FPGAs must be Virtex-5 LX330T or higher capacity. Other than that nothing much is actually required. I have been searching for such a board but most of them ar...


Configuration : Virtex-E, CLB column

Started by Cyrille Lambert in comp.arch.fpga17 years ago

Dear all, Subject: Virtex-E, CLB column. Inside a Xilinx Virtex-E FPGA, 5 types of column are present (Centre, CLB, Block SelectRAM...

Dear all, Subject: Virtex-E, CLB column. Inside a Xilinx Virtex-E FPGA, 5 types of column are present (Centre, CLB, Block SelectRAM Interconnect, Block SelectRAM Content, Right-Left IOB Columns). Let's take in account the CLB column. Each CLB column contains 2 Top IOB blocks, 2 Bottom IOB blocks and a certain number of "CLB" blocks. Each "CLB" block contains the information about t


USB host

Started by Mich in comp.arch.fpga15 years ago

Hi, I want to connect a webcame to a Virtex II pro and do some real time processing on it. Can someone give me some tips how to use a Virtex...

Hi, I want to connect a webcame to a Virtex II pro and do some real time processing on it. Can someone give me some tips how to use a Virtex II pro as an USB host? Greets Mich


Virtex II Pro Config

Started by maxascent in comp.arch.fpga15 years ago

Hi I am looking at ways to configure a Virtex II Pro Device. I want to add some Flash memory for use with the PPC Core and was wondering if I...

Hi I am looking at ways to configure a Virtex II Pro Device. I want to add some Flash memory for use with the PPC Core and was wondering if I could store the config data in some of it? If I can how would I go about interfacing to it. Thanks Jon


Virtex-4 driving a 5V CMOS

Started by fpgauser in comp.arch.fpga13 years ago 6 replies

Hi all, I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything wrong with simply using a pullup to 5V? The speed...

Hi all, I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything wrong with simply using a pullup to 5V? The speed doesn't matter. Thanks.


order

Started by akohan in comp.arch.fpga11 years ago 1 reply

hi group, In following page, in what order should I start to learn about Virtex 4 ? ...

hi group, In following page, in what order should I start to learn about Virtex 4 ? http://www.xilinx.com/support/documentation/virtex-4_user_guides.htm Thanks, Amit


One bit Virtex BRAM.

Started by Jacques athow in comp.arch.fpga17 years ago 3 replies

Is it possible to infer in vhdl, some kind of logic that has the same property as that of a virtex block ram, but being of size 1 bit...

Is it possible to infer in vhdl, some kind of logic that has the same property as that of a virtex block ram, but being of size 1 bit (just using CLB logic) ?? Thanks for any ideas jac