ModelSim XE problems with a VHDL coregen in a Virtex 5

Started by Dan K in comp.arch.fpga13 years ago 1 reply

I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is...

I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I see these files in the $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the ModelSim workspace under xilinxcorelib which only goes up to blk_mem_gen_v2_4. Does anyone kn...


Xilinx ML403 Virtex 4 IIC uses bitbang test?

Started by Newman in comp.arch.fpga15 years ago 1 reply

I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluation core to communicate...

I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluation core to communicate with an IIC EEPROM. OK, that sounds reasonable. There are also numerous demo programs that show off the board and Virtex 4 capabilities, which sounds reasonable. Further investigation shows that the iic_eeprom demo program bypasses the IIC core in the...


Virtex-4 BSCAN

Started by David R Brooks in comp.arch.fpga15 years ago 2 replies

The Virtex-4 data sheet states that the BSCAN module can support 4 user-data registers. However there is an Errata sheet which states that...

The Virtex-4 data sheet states that the BSCAN module can support 4 user-data registers. However there is an Errata sheet which states that early (ES) parts only supported one register. The "Virtex-4 Libraries Guide for HDL Designs" shows a BSCAN_VIRTEX4 element supporting only one user register (although it mentions USER1 & USER2 instructions, suggesting two registers). The librar...


problem with using DCM of virtex 4

Started by farhanakram in comp.arch.fpga11 years ago

I am using the DCM of the Virtex 4VSX35 to make the 100MHz pulse from the 50MHz but results are not satisfactory instead of having (1010) from...

I am using the DCM of the Virtex 4VSX35 to make the 100MHz pulse from the 50MHz but results are not satisfactory instead of having (1010) from the resultant pulse i am getting (1xx0) can anybody tell me how to get my desired result. --------------------------------------- Posted through http://www.FPGARelated.com


Virtex 5 LVDS

Started by maxascent in comp.arch.fpga12 years ago 8 replies

Hi I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to invert the signal so that I can have P-> N and N-> P on the...

Hi I am routing a pcb with some LVDS signals. Is there a way in Virtex 5 to invert the signal so that I can have P-> N and N-> P on the pcb. Cheers Jon


Virtex-II Pro and DDR2 SDRAM differential IO

Started by bob in comp.arch.fpga17 years ago

I'm doing a Virtex-II Pro design that uses DDR SDRAM SODIMM modules as data storage. There's a possibility (because DDR and DDR2 SODIMMs...

I'm doing a Virtex-II Pro design that uses DDR SDRAM SODIMM modules as data storage. There's a possibility (because DDR and DDR2 SODIMMs are footprint compatible) to support the upcoming DDR2 modules in this design too. Now, there's a problem: DDR2 SDRAM supports the use of differential signaling on data strobe lines (DQS). However, these signals are still 1.8V SSTL. Virtex-II Pro device (...


pricing of Virtex-4

Started by Vladislav Muravin in comp.arch.fpga16 years ago 6 replies

Hello, Can anybody give me an estimate price range of the two smallest Virtex-4 devices, namely LX15 and LX25? I am interested in the lowest...

Hello, Can anybody give me an estimate price range of the two smallest Virtex-4 devices, namely LX15 and LX25? I am interested in the lowest speed grade and SF363 package. I have been trying to get it from distributor for the past few weeks and ... Thank you all for your time and attention. Sincerely, Vladislav


What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L

Started by Weng Tianxiang in comp.arch.fpga14 years ago 8 replies

Hi, When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would like to know which patents filed by Xilinx to disclose the contents...

Hi, When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would like to know which patents filed by Xilinx to disclose the contents of Slice L. Slice M is too complex for me to fully understand at the moment and just knowledge of Slice L is good enough for me to start with Virtex-5 as basic knowledge for it. Thank you. Weng


Configuration-Frames for Virtex-II (Pro)

Started by Sven in comp.arch.fpga16 years ago 1 reply

Hi, I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro) architecture. On...

Hi, I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro) architecture. On Xilinx websites I just find informations about the configuration-memory-addressing for these architectures and some informations for the Virtex architecture, but i`m intressted in the meaning of the bits in the frames. Can anybody help me? At the mom...


best evm for virtex-4 and linux

Started by Anonymous in comp.arch.fpga15 years ago 18 replies

Can anyone suggest the best evm board for virtex-4 and linux? How has people's experience been with it? Are USB drivers included in the linux...

Can anyone suggest the best evm board for virtex-4 and linux? How has people's experience been with it? Are USB drivers included in the linux os builds they provide? Thanks, Clark


Virtex DeviceSimulator

Started by h230184 in comp.arch.fpga16 years ago

Hi. I'm a newbie to fpga design and I'd like to know whether it's possible to simulate the behaviour of a bitstream generated with ISEWebPack...

Hi. I'm a newbie to fpga design and I'd like to know whether it's possible to simulate the behaviour of a bitstream generated with ISEWebPack without implementing it on board. Can I use for this the Virtex DeviceSimulator? Where can I download it? And i'd also like to test on my computer a vhdl program that writes some stuff to screen. Is it possible? Thanks a lot.


Virtex-5 FXT coming soon?

Started by Antti in comp.arch.fpga13 years ago 10 replies

Hi, the fact that forum posting about ML507 was removed by Xilinx moderator (from Xiliinx forums), gives us at least the information that...

Hi, the fact that forum posting about ML507 was removed by Xilinx moderator (from Xiliinx forums), gives us at least the information that ML507 is a Virtex-5FXT development board. This should mean that the FXT silicon will soon be announced. Sure many of us hoped FXT some years ago already. Antti


Linux 2.6 PCI Device Driver on Virtex 4

Started by Anonymous in comp.arch.fpga13 years ago 2 replies

I have spent the past few months slowly trying to get a PCI design with Linux 2.6 on the Virtex 4. I have been able to overcome some of the...

I have spent the past few months slowly trying to get a PCI design with Linux 2.6 on the Virtex 4. I have been able to overcome some of the hurdles; however, I am still unable to boot up a working system. If anyone has tried to do this (or has already done this) I would apprecaite any help or suggestions. I can go into more detail as to what I have done and where I am stuck if there is anyon...


Xilinx Virtex-4 BRAM-16 Simulation

Started by Brad Smallridge in comp.arch.fpga15 years ago 13 replies

Does anyone have a Virtex-4 BRAM16 simulation running? I have been trying for two days now to get a simulation to work to no avail using...

Does anyone have a Virtex-4 BRAM16 simulation running? I have been trying for two days now to get a simulation to work to no avail using coregen, primitives, ISE simulator and ModelSim_XE. Brad Smallridge aivision dot com


Amount of wire and logic

Started by Pasacco in comp.arch.fpga14 years ago 21 replies

Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) There is a constant...

Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) There is a constant ratio of INTERCONNECT to LOGIC. (2) When amount of LOGIC increases N times, amount of INTERCONNECT increases N times. For example : Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains 44096 slices. That is, Virtex-II Pro-100 conta...


Reed solomon IP core

Started by nezhate in comp.arch.fpga13 years ago 2 replies

Hi all, Looking at the Xilinx IP core documentation I found only 2 versions of reed solomon decoder implemented on Virtex-5 (RS decoder version...

Hi all, Looking at the Xilinx IP core documentation I found only 2 versions of reed solomon decoder implemented on Virtex-5 (RS decoder version 6.1) and Virtex-2pro (RS decoder version 5.1). I need to know how this IP core will consume (LUTs, slices, Block RAM/FIFO, Frequency) if it is implemented on virtex-4 (xc4vfx12-10ff668 or XC4vlx100-11ff668). Any documentation will be helpful. Thank ...


Virtex-4 & Wifi

Started by zcsi...@gmail.com in comp.arch.fpga14 years ago 1 reply

Hi All, What is the easiest/best approach to attach Wifi to Virtex-4 (using from Linux)? Id' like to use some longer range/higher rate wifi...

Hi All, What is the easiest/best approach to attach Wifi to Virtex-4 (using from Linux)? Id' like to use some longer range/higher rate wifi module (eg. atheros). Any suggestions/ideas/eval boards? Regards, Zoltan


Virtex "Virtual VCC"

Started by lenz in comp.arch.fpga18 years ago 3 replies

Hi ! I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel connector. The Virtex is connected to the SCSI-2 style front...

Hi ! I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel connector. The Virtex is connected to the SCSI-2 style front panel connector with 68 pins.These pins are interleaved signal and ground pairs.So, I have 34 free I/O at the front panel connector. I would like to connect a little add-on board to this front panel connector. This board will be populated with a Gigabi...


Virtex-5 User Guide "Lite"

Started by Peter Alfke in comp.arch.fpga13 years ago 2 replies

If you want to get a feel for what you can do with Virtex-5, click...

If you want to get a feel for what you can do with Virtex-5, click on http://www.pldesignline.com/howto/206503253;jsessionid=S30OVRH051RUYQSNDLPCKH0CJUNN2JVN This was a labor of love. Something like it should have been written ten years ago, but: "Better late than never". Hope you like it, and can draw some benefit from it. Please don't hesitate to post or send me comments of any kind. ...


Parallel port to Virtex 2 level converter chip, anyone?

Started by Lin MuIin in comp.arch.fpga16 years ago 1 reply

I am looking for the simplest Parallel port to virtex 2 IO voltage converter. I would like to use the default Virtex 2 IO standard which...

I am looking for the simplest Parallel port to virtex 2 IO voltage converter. I would like to use the default Virtex 2 IO standard which is used by ISE (Is it LVCMOS33?) I was aware that normal level converter output voltage follows the power supply and I don't want to trouble having a 3.3V power supply. Thank?you.?