Using RiscWatch with Xilinx FPGA's for powerpc

Started by Pankaj in comp.arch.fpga15 years ago 1 reply

Using RiscWatch with Xilinx FPGA's for powerpc. I have Xilinx 7.1 package with xilinx fpga boards , as well ML310 with virtex 2p devices ,on...

Using RiscWatch with Xilinx FPGA's for powerpc. I have Xilinx 7.1 package with xilinx fpga boards , as well ML310 with virtex 2p devices ,on which powerpc and microblaze architectures are supported. I wanted to run an application on this powerpc architecutre and debug it. As i am using powerpc so i think risc watch debugger would be better. But my question is does xilinx provide support ...


Xilinx multiplier out of slices

Started by Peter Sommerfeld in comp.arch.fpga16 years ago 4 replies

Hi, I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise the following statement: y

Hi, I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise the following statement: y


Latest Xilinx Software

Started by 2cents in comp.arch.fpga10 years ago 1 reply

Did anyone see this video of 13.1? https://xilinx.webex.com/xilinx/lsr.php?AT=pb&SP=EC&rID=3372608&rKey=38aaf4d8e5851be5 Looks like a big leap...

Did anyone see this video of 13.1? https://xilinx.webex.com/xilinx/lsr.php?AT=pb&SP=EC&rID=3372608&rKey=38aaf4d8e5851be5 Looks like a big leap forward...


Perl + Xilinx + commandline = Module::Build::Xilinx

Started by vicash in comp.arch.fpga7 years ago 4 replies

Hello I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. (https://metacpan.org/pod/Module::Build::Xilinx) This is a...

Hello I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. (https://metacpan.org/pod/Module::Build::Xilinx) This is a tool that you can use to create a simple makefile like Build.PL script such as done by standard perl modules. Module::Build::Xilinx subclasses Module::Build to create, build, simulate, view and program Xilinx FPGA development boards by using Perl to m...


Xilinx ISE 11.1 crash - Visual Studio error

Started by Daku in comp.arch.fpga11 years ago 4 replies

Could some Xilinx ISE guru provide some hints for my problem ? I am trying to synthesize a simple 4K RAM block with Xilinx ISE. About half- way...

Could some Xilinx ISE guru provide some hints for my problem ? I am trying to synthesize a simple 4K RAM block with Xilinx ISE. About half- way through execution, I get an error message, inside a Visual Studio dialog box, stating that xst.exe ( the Xilinx synthesis executable) has encountered a problem and would I like to debug ? The Xilinx ISE is running on a XP machine. Any hints, suggest...


problem generate PCI-32/66MHz with Coregen

Started by Anonymous in comp.arch.fpga14 years ago 3 replies

Coregen report me: DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zip.ZipException:...

Coregen report me: DEBUG[cmsg] - EJava Unzip Failure on v3.0.160.zip for D:\Xilinx\testCOREGEN\tmp\_cg\_bbxjava.util.zip.ZipException: Not enough disk space in path, D:\Xilinx\testCOREGEN\tmp\_cg\_bbx, to uncompress all files in ZIP/JAR file: c:\Xilinx\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v3_160\fileset\v3.0.160.zip. DEBUG[cmsg] - CopyFilesetZip:: srcFileDir: v3.0.160 ERROR:coreu...


Problem with Xilinx FTP

Started by Hendra in comp.arch.fpga15 years ago 1 reply

What happens to Xilinx ftp with the following URL ftp://ftp.xilinx.com/pub/ftpfiles.htm Most of the files can not be downloaded. Have they...

What happens to Xilinx ftp with the following URL ftp://ftp.xilinx.com/pub/ftpfiles.htm Most of the files can not be downloaded. Have they been moved? If they have, where is the new URL? Hendra


Xilinx: Where has all the data gone?

Started by Gabor in comp.arch.fpga16 years ago 1 reply

Browsing the Xilinx website documentation I seem to get no data sheets, user guides, or package drawings. Just: Sorry... Technical...

Browsing the Xilinx website documentation I seem to get no data sheets, user guides, or package drawings. Just: Sorry... Technical difficulties with the Xilinx.com web site have been solved. If you are continuing to have difficulty accessing Xilinx.com, you may need to exit your browser software and restart it. Please accept our apologies for any difficulties you have experienced. I tr...


What equivalent attribute in Xilinx IDE

Started by fl in comp.arch.fpga5 years ago

Hi, I see an example on Xilinx FPGA with tool Synplify-Pro: attribute syn_multstyle : string; attribute syn_multstyle of MULT : signal is...

Hi, I see an example on Xilinx FPGA with tool Synplify-Pro: attribute syn_multstyle : string; attribute syn_multstyle of MULT : signal is "logic"; I only have Xilinx IDE. How can I get the above constraint in IDE? I am working on Xilinx Spartan-6. Thanks,


Xilinx VSK (Video Starter Kit)

Started by dakkumar in comp.arch.fpga14 years ago 2 replies

I would like to exchange information on the Xilinx VSK with others using the kit. In particular I have the following observations: A1. The...

I would like to exchange information on the Xilinx VSK with others using the kit. In particular I have the following observations: A1. The VSK provides no help to people who do not wish to invest in (a) Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible with 8.1. VSK assumes that anyone buying VSK will also buy these packages, or has them already. A2. Xilinx should...


Xilinx System Generator crashes repeatedly

Started by Anonymous in comp.arch.fpga15 years ago 2 replies

I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/Xilinx System Generator...

I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/Xilinx System Generator 8.1.01 software installation. My problem is that the Xilinx Simulink blockset is entirely unstable. For example, when I try to change the properties of any Xilinx block, the Java runtime often crashes and takes MatLab with it. All other non-Xilinx bl...


Xilinx System Generator crashes repeatedly

Started by Anonymous in comp.arch.fpga15 years ago

I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/Xilinx System Generator...

I am sorry for posting this as I have already posted it on the comp.soft-sys.matlab. I have a MatLab 7.2/Simulink 6.4/Xilinx System Generator 8.1.01 software installation. My problem is that the Xilinx Simulink blockset is entirely unstable. For example, when I try to change the properties of any Xilinx block, the Java runtime often crashes and takes MatLab with it. All other non-Xilinx bl...


Nuhorizons alternatives for Xilinx parts?

Started by dlharmon in comp.arch.fpga16 years ago 1 reply

I am currently doing work on a small board with a FPGA and DSP. I have been planning to use the Xilinx XC3S1000-4FT256C , but...

I am currently doing work on a small board with a FPGA and DSP. I have been planning to use the Xilinx XC3S1000-4FT256C , but Nuhorizons doesn't seem too interested in selling me 2 for a prototype. Where else could I find these? The Xilinx online store only has parts up to the XC3S400. I have checked digikey, but they are a few years behind on the Xilinx parts. I may have to consider c...


a clueless bloke tells Xilinx to get a move on

Started by Brannon in comp.arch.fpga14 years ago 29 replies

The following is an informal letter to Xilinx requesting their continued efforts to increase the speed of their software tools. If there are...

The following is an informal letter to Xilinx requesting their continued efforts to increase the speed of their software tools. If there are incorrect or missing statements, please correct me! Dear Xilinx: As many of us spend numerous hours of our life waiting for Map/Par/Bitgen to finish, I hereby petition Xilinx, Inc., to consider this issue (of their tool speed) to be of the highest p...


xdl tool, or Xilinx Design Language

Started by Mahim Mishra in comp.arch.fpga16 years ago 1 reply

Hello all, Does anyone know where I can find documentation on the text output format of the xdl tool (which I believe is what Xilinx calls...

Hello all, Does anyone know where I can find documentation on the text output format of the xdl tool (which I believe is what Xilinx calls the Xilinx Design Language)? I have looked on the Xilinx website and on the web, and not found anything useful. Any pointers will be greatly appreciated. Thanks, Mahim


XILINX Ethernet MAC (URGENT...)

Started by vikram in comp.arch.fpga13 years ago 5 replies

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet...

hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet MAC ip core. i must admit i am very new to such work, forgive my blatantness.... i would like to know: 1) What exactly do i get in the Xilinx Ethernet MAC ip core? (design files etc?) 2) Using XPS (EDK 9.1) and ISE 9.1, how do i integrate it int...


Anybody understand this ISE 7.1 error, and what to do about it???

Started by Andrew Lohbihler in comp.arch.fpga15 years ago 25 replies

Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or what to do about it. Any help...

Hi, I had this error in Xilinx ISE 7.1 but I cannot understand why, or what to do about it. Any help appreciated. Thanks, -Andrew Release 7.1.04i Map H.42 Xilinx Mapping Report File for Design 'xilinxchip_original' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -ise c:\xilinx\bin\pv4_004mfsd_127\original.ise -intstyle ise -p xc4vlx60-ff668-12 -c...


Problems with Xilinx Parallel III Cable

Started by Anonymous in comp.arch.fpga14 years ago 20 replies

Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a programmer to use the...

Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a programmer to use the Xilinx Parallel Cable III. I implemented the programmer 100% the same as found in Xilinx's website ( http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html). The programmer worked, but not without problems. For programming the Atmel uC I us...


Altium DXP for designing Xilinx FPGA

Started by Dieter Keldenich in comp.arch.fpga17 years ago 7 replies

Hi, does anybody have experience in using Altium DXP for designing Xilinx FPGA? Is it possible to compile Xilinx libraries...

Hi, does anybody have experience in using Altium DXP for designing Xilinx FPGA? Is it possible to compile Xilinx libraries (unisim/coregenlib/simprim) for using them in DXP? DXP is not supported by Xilinx, what are the risks in using it? kind regards Dieter Keldenich


Where is the xilinx online store gone?

Started by Anonymous in comp.arch.fpga15 years ago 37 replies

Hi everyone, As I was buying some components from the Xilinx online store this morning, I noticed that they no longer support silicon device...

Hi everyone, As I was buying some components from the Xilinx online store this morning, I noticed that they no longer support silicon device anymore. It seems that it is now AVNET that is taking care of distributing Xilinx FPGA online. The worse thing is that the price is more expensive, and they do not have all the parts that Xilinx use to offer (the part I am looking for specially). Now...