How to resolve a Xilinx 8.1 BlockRAM problem

Started by Weng Tianxiang in comp.arch.fpga14 years ago 4 replies

Hi, I need your help. My project uses BlockRAM by Xilinx. I used CoreGenerator 6.2 to generate BlockRAM bram64_8, and Xilinx free 8.1 ISE...

Hi, I need your help. My project uses BlockRAM by Xilinx. I used CoreGenerator 6.2 to generate BlockRAM bram64_8, and Xilinx free 8.1 ISE version. By using code generated for ModelSim simulation, it works well without any error. But while compiling with Xilinx 8.1 ISE, it generates the following errors: ERROR:NgdBuild:604 - logical block 'MG_x_A3/bram64_8_A/BU5' with type 'RAM...


xilinx+modelsim total newbie

Started by Anonymous in comp.arch.fpga16 years ago 1 reply

Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free edition. I need Xilinx for my digital circuits course. During the course...

Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free edition. I need Xilinx for my digital circuits course. During the course laboratory we were using Xilinx foundation 2.1. After designing simple circuit I have attached some probes to inputs and output and then in simulator bound some keys in order to change input signals' from 0 to 1 and test the output. The problem is I don...


ERROR: overlaps section...

Started by charlie78 in comp.arch.fpga12 years ago 3 replies

Hi all, XPS 10.1 returns me these...

Hi all, XPS 10.1 returns me these errors... /cygdrive/c/Programmi/Xilinx/10.1/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1 .1/../../../../microblaze-xilinx-elf/bin/ld.real: region ilmb_cntlr_dlmb_cntlr is full (TestApp_Memory/executable.elf section .text) /cygdrive/c/Programmi/Xilinx/10.1/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1 .1/../../../../microblaze-


Missing Xilinx EDK Temac example

Started by Paul Tobias in comp.arch.fpga14 years ago

On Xilinx's website page: http://www.xilinx.com/ise/embedded/edk_examples.htm There are 2 LWIP EDK example designs, one of which is supposed...

On Xilinx's website page: http://www.xilinx.com/ise/embedded/edk_examples.htm There are 2 LWIP EDK example designs, one of which is supposed to support the hard Gigabit temac core on the Virtex 4 FX series. In fact, both zip files are identical and for the 10/100 soft core. Has anybody found the Temac example, or heard from Xilinx whether the Temac example will be out with the next ...


Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii yee

Started by Antti in comp.arch.fpga12 years ago 9 replies

Hi :) for many years Xilinx has tried to HIDE the schematics of the USB Cable, but as of today Xilinx has made it public !!! really good...

Hi :) for many years Xilinx has tried to HIDE the schematics of the USB Cable, but as of today Xilinx has made it public !!! really good news, no more guessing needed http://www.xilinx.com/support/answers/33028.htm from this page get the archieve, look in the schematics page 14 Antti


Xilinx xapp802.pdf mistake?

Started by David Ashley in comp.arch.fpga14 years ago 3 replies

Mostly for xilinx people, xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available...

Mostly for xilinx people, xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available here: http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf#search=%22xilinx%20ddr%20fae%22 On page 3 is figure 2. There is an FDDR shown on the diagram that has left and right data going into the D0 and D1 inputs, but both clocks are coming from the same source (CLK0 from the DCM). S...


Xilinx tcl: How to determine if a process fails

Started by Anonymous in comp.arch.fpga13 years ago

Hi, After no response in the xilinx forums, I thought I'd post my problem here to see if anyone has any ideas. I have an xtclsh script that...

Hi, After no response in the xilinx forums, I thought I'd post my problem here to see if anyone has any ideas. I have an xtclsh script that I'm using to implement a Xilinx FPGA design using ISE. I'm having a problem determining if a synthesis error occurred: ########################################\n Script 1: project open build/xilinx/$target/$target.ise #(set device propertie


System Generator.

Started by Anonymous in comp.arch.fpga16 years ago 2 replies

Friends, I was trying to install Xilinx System Generator v 6.2 (evaluation) on my computer. I have Xilinx webpack 6.2i SP 3 with IP Update 1.1...

Friends, I was trying to install Xilinx System Generator v 6.2 (evaluation) on my computer. I have Xilinx webpack 6.2i SP 3 with IP Update 1.1 for it & Matlab 6.5 (R13) But while installing it says "Can not find Code GENERATOR" installation. i checked environmet variable, XILINX = c:\Xilinx & that's where my installation is. Any Suggetions? Thanks Nirav


AVNET Xilinx Spartan3 board, example problem

Started by Monica in comp.arch.fpga16 years ago 2 replies

Hi all, I am Monica from Germany,I am new to FPGA programming.I have very little experience with Altera cyclone FPGA development and...

Hi all, I am Monica from Germany,I am new to FPGA programming.I have very little experience with Altera cyclone FPGA development and Quartus software.I dont have any experience with Xilinx tools.Now our company want to try Xilinx because xilinx offers J.83 Annex A/C Modulator QAM IP core. We have received a AVNET Xilinx Spartan3 board with xc3s1500 FPGA.Our company wants me to test the ...


Synthesizing Xilinx Coregen cores

Started by Anonymous in comp.arch.fpga14 years ago 1 reply

Hey every1, I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v xilinx file. When i try synthesise everything with...

Hey every1, I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v xilinx file. When i try synthesise everything with Leonardo Spectrum it errors out: "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 671: Warning, system task enable ignored for synthesis "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 700: Warning, initial statement not supported. Ignore...


simulating Xilinx cores

Started by FPGA in comp.arch.fpga13 years ago 1 reply

I would like to simulate some modules in Verilog along with a FIFO generated by ISE core. I would like to know if it is possible to simuate teh...

I would like to simulate some modules in Verilog along with a FIFO generated by ISE core. I would like to know if it is possible to simuate teh Xilinx generated cores. If so, which tools do I need to use for that? Is there a free Xilinx simulator I could use to sereve the purpose? I was using Modelsim till date. I dont think Modelsim would recognize the Xilinx cores. Your comments would be a...


Xilinx Core Gen Question

Started by Laurent Gauch in comp.arch.fpga16 years ago 3 replies

Hi all, Can I insert my own IP core in the Xilinx Core Gen? Can I use Xilinx Core Gen to manage my OWN VHDL IP core? If not, why Xilinx does...

Hi all, Can I insert my own IP core in the Xilinx Core Gen? Can I use Xilinx Core Gen to manage my OWN VHDL IP core? If not, why Xilinx does not allow that feature. Larry, www.amontec.com


Xilinx tools for XC3020???

Started by Mike Butts in comp.arch.fpga8 years ago 14 replies

I've got a 20-year-old Xilinx XC3020 development board. I think it would be fun to fire it up and bring it to the 20th anniversary FCCM in Seattle...

I've got a 20-year-old Xilinx XC3020 development board. I think it would be fun to fire it up and bring it to the 20th anniversary FCCM in Seattle next month. (http://fccm.org/2013/) I don't see XC3000-series supported on even the oldest archived ISE at xilinx.com. Anyone know where I can find some tools for this old chip? It has 64 CLBs and 256 flip-flops! Maybe one of you folks at Xilinx? Tha...


Going insane - Xilinx VGA controller...

Started by pete...@alarmip.com in comp.arch.fpga15 years ago 13 replies

Dear Group, I am designing an LCD controller, straight VGA using a 6.5" TFT (60Hz and a 25MHz dot clock) with a 32MBit SDRAM frame buffer...

Dear Group, I am designing an LCD controller, straight VGA using a 6.5" TFT (60Hz and a 25MHz dot clock) with a 32MBit SDRAM frame buffer (using two Xilinx block RAMs as alternate line buffers). Xilinx ISE 7.1 development environment. I also designed the hardware: a BlackFin BF532 CPU/ROM/SDRAM with a Xilinx Spartan-3 (XC3S400-4PQ208C) handling the general I/F requirements and VGA dis...


[SPARTAN-3]: Parts Back on Xilinx Online Store (www.xilinx.com/store)

Started by Steven K. Knapp in comp.arch.fpga16 years ago 4 replies

As promised last week, Xilinx Spartan-3 FPGAs (XC3S50 through XC3S400) are back on the Xilinx online store and in...

As promised last week, Xilinx Spartan-3 FPGAs (XC3S50 through XC3S400) are back on the Xilinx online store and in stock. http://www.xilinx.com/store My apologies for any inconvenience that this might have caused. The devices available online are all from the new 300 mm wafer production line. The change-over caused a momentary hiccup in the store data base. -------------------------------...


Went from Xilinx to Altera: Cyclone-II and I/O pullup?

Started by Xilinx user in comp.arch.fpga14 years ago 2 replies

I'm a longtime Xilinx user, and I've recently switched over to the dark side :) Anyway, I'm new to Quartus-II Web Edition, and I'm trying to...

I'm a longtime Xilinx user, and I've recently switched over to the dark side :) Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a project from my Xess XSA-3S1000 board to a Altera Cyclone-II Starter Kit. I've run into a problem where I have bidi I/Os which need a PULLUP. The Xilinx Spartan-3's I/Os supported a PULLUP constraint, specified in Xilinx's *.UCF file. I sea...


Xilinx XPS crash on Linux

Started by pes in comp.arch.fpga11 years ago 2 replies

Hi, I want to test Microblaze processor with Xilinx tools. After creating a MicroBlaze project with the Xilinx Platform Studio, the...

Hi, I want to test Microblaze processor with Xilinx tools. After creating a MicroBlaze project with the Xilinx Platform Studio, the application crashes. Same crash happens when I open this project. I use Mandriva 2010 32b and Xilinx support doesn' t help me since I have an unsupported OS. I get this message with $dmesg after the crash : xpsgui[21688]: segfault at 5 ip b60a2f38 s...


xilinx usb cable

Started by chinnathurai in comp.arch.fpga11 years ago 1 reply

which cypress tool is used to read or write the PID,VID in EEPROM in xilinx usb programmer? I want to read the PID,VID from xilinx spartan-3E...

which cypress tool is used to read or write the PID,VID in EEPROM in xilinx usb programmer? I want to read the PID,VID from xilinx spartan-3E starter kit how can i do that? --------------------------------------- Posted through http://www.FPGARelated.com


since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)

Started by mikelinyoho in comp.arch.fpga15 years ago 2 replies

regards: since xilinx ise 8.1i support linux red hat 4.0 (with device Spartan-3 400k) After I install xilinx ise 8.1 under linux red hat...

regards: since xilinx ise 8.1i support linux red hat 4.0 (with device Spartan-3 400k) After I install xilinx ise 8.1 under linux red hat 4.0,I cannot find a icon to start the software "xilinx ise 8.1i".Someone say that I might start xilinx ise 8.1i at linux red hat 4.0 command mode.Is this saying right? and how can I achieve that "start xilinx ise 8.1i at linux red hat 4.0" any positiv...


Suse 9.1 Linux and Xilinx ISE 6.2i

Started by salman sheikh in comp.arch.fpga17 years ago 22 replies

Hello, I just installed Xilinx ISE 6.2i on a Linux box and it is sluggish as anything. Does anyone know why? I am running on a P4 1.7GHz w/...

Hello, I just installed Xilinx ISE 6.2i on a Linux box and it is sluggish as anything. Does anyone know why? I am running on a P4 1.7GHz w/ 1GB of RAM. On windows, it is much more zippy. Could it be the gui toolkit that Xilinx is using (it seems like JAVA.......slow as a slug....)? Thanks. Salman