Xilinx Virtex II Pro: LVDS_25 vs. BLVDS_25

Started by eNo in comp.arch.fpga17 years ago 1 reply

Anyone know the difference between LVDS_25 and BLVDS_25 in Xilinx's Virtex II Pro or point me to a spec. where I can read about the...

Anyone know the difference between LVDS_25 and BLVDS_25 in Xilinx's Virtex II Pro or point me to a spec. where I can read about the electrical characteristics of these two? Searching through Xilinx.com has yielded zero. [When I set IOSTANDARD=BLVDS_25 for some of my differential (OBUFDS) outputs, I get an Exception during mapping in Xilinx's ISE 6.1.03i. LVDS_25 works fine for all my differen...


What is this ASMBL thing from Xilinx?

Started by Rahul Khanna in comp.arch.fpga17 years ago 5 replies

Xilinx seems to have launched a new architecture - ASMBL. There is no information except a news article. Can we have more info??? Is anyone from...

Xilinx seems to have launched a new architecture - ASMBL. There is no information except a news article. Can we have more info??? Is anyone from Xilinx Listening????


ROM instantiation question

Started by D in comp.arch.fpga17 years ago 2 replies

Problems keeping instantiated ROM in Xilinx XST. Say I have a rom named rom16x16. It consists of 16 - 16x1 ROM primitive instantiations from...

Problems keeping instantiated ROM in Xilinx XST. Say I have a rom named rom16x16. It consists of 16 - 16x1 ROM primitive instantiations from the xilinx library. How do I force xilinx to keep this ? The code is being combined into only one ROM (even though I have "init'd" the ROMS to different values. I tried using "keep heirarchy" under synthesis properties but that was a no go. I'm ...


Xilinx device not listed

Started by FP in comp.arch.fpga12 years ago 5 replies

Hello, I have a quick question. I dont see Xilinx Virtex -5 sx95t device in the list of devices in Xilinx ISE and CoreGen. How do I fix...

Hello, I have a quick question. I dont see Xilinx Virtex -5 sx95t device in the list of devices in Xilinx ISE and CoreGen. How do I fix this issue? I have unistalled and reinstalled ISE. Your comments would be appreciated.


Partial Reconfiguration

Started by ram in comp.arch.fpga17 years ago 4 replies

Hi all, I am interested in doing partial reconfiguration using Xilinx Virtex 2 pro, i am having a HW AFX xilinx prototype baord. I tried the...

Hi all, I am interested in doing partial reconfiguration using Xilinx Virtex 2 pro, i am having a HW AFX xilinx prototype baord. I tried the small bit manipulation method defined in Xilinx application note xapp290, with the simple example , Example 1 simple system desing from xilinx EDK examples web page. Ok , my desing is this, I am using PPC405, and uartlite and gpio with uart contin...


modular design flow in Xilinx ISE 6.1.

Started by Ian in comp.arch.fpga17 years ago 1 reply

Hello All, I am having problems running the modular design flow in Xilinx ISE 6.1. Everything seems OK until I configure (Spartan2 via...

Hello All, I am having problems running the modular design flow in Xilinx ISE 6.1. Everything seems OK until I configure (Spartan2 via Boundary Scan /Parallel using Impact) I get a programming failed message - the done pin failed to go high. I have tried a few different options in Bitgen with no success. Also, the Xilinx ISE 'development systems reference guide' and the Xilinx answer...


Xilinx Webpack vs Foundation ?

Started by Roger Bourne in comp.arch.fpga15 years ago 4 replies

Hello all, What is the MAIN difference between Xilinx ISE Foundation and Xilinx ISE WebPACK ? Can they both do FPGA design, simulation, place...

Hello all, What is the MAIN difference between Xilinx ISE Foundation and Xilinx ISE WebPACK ? Can they both do FPGA design, simulation, place and route, and post-place and route simulations ? They both seem to support the Xilinx FPGAs -Roger


xilinx virtex 2 multimedia board ( XC2V2000)

Started by mike in comp.arch.fpga15 years ago

Hi I am a student and trying my hands off xilinx virtex 2 multimedia board. I was trying to run an example "Character Mode SVGA" from...

Hi I am a student and trying my hands off xilinx virtex 2 multimedia board. I was trying to run an example "Character Mode SVGA" from xilinx website http://www.xilinx.com/products/boards/multimedia/examples.htm I am able to download the bit file to the board but now what do i do ? how do i see the picture on the computer screen ? i am bit lost , i tried to simulate the design using mo...


Xilinx Legal

Started by Austin Lesea in comp.arch.fpga15 years ago 48 replies

All: From our legal group- "Xilinx invests a significant amount in research and development, and vigorously protects and enforces its...

All: From our legal group- "Xilinx invests a significant amount in research and development, and vigorously protects and enforces its intellectual property rights resulting from its research and development efforts. It is also correct that when Xilinx licenses its software and tools, Xilinx prohibits its customers from reverse engineering and decompiling its software products. Also, ...


Xilinx cable drivers for Linux 2.6.16?

Started by Wojciech Zabolotny in comp.arch.fpga15 years ago 1 reply

Has anybody managed to compile the Xilinx cable drivers for Linux kernel 2.6 available here:...

Has anybody managed to compile the Xilinx cable drivers for Linux kernel 2.6 available here: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22648 ftp://ftp.xilinx.com/pub/utilities/M1_workstation/linuxdrivers.2.6.tar.gz with kernel 2.6.16? The problem is with windrvr6 driver. After ./configure and ./make I get a bunch of errors: /lib/modules/2.6.16.18/build/include/asm/rwsem...


Regarding Xilinx tool

Started by vignesh_karthi in comp.arch.fpga13 years ago 2 replies

My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can i create the *.ucf...

My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can i create the *.ucf file using xilinx Tool ? (if you have provide me ) 2. how can i avoid the multicycle path and false path ? (if you have provide me ) 3. Do you have any basic user manual for xilinx tool ? (if you have provide me ) Advanced Thanks to you......


WANTED: Contract Verilog Designer

Started by Anonymous in comp.arch.fpga15 years ago

We have an immediate requirement for a Verilog designer for a short-term (approx. 3 month) period. This job involves completing two projects...

We have an immediate requirement for a Verilog designer for a short-term (approx. 3 month) period. This job involves completing two projects already underway. Both projects are embedded communications systems. In both cases the targets are Xilinx Spartan 3 FPGAs. In one case the design includes the Xilinx Microblaze soft processor. The tool chain is Synplify, Xilinx EDK and Xilinx IS...


Xilinx and Lattice tools on one machine?

Started by Gabor in comp.arch.fpga15 years ago 2 replies

Does anyone have experience running tools from Xilinx (ISE, XST) and Lattice (ispLever) on the same Windows computer? I've had problems in the...

Does anyone have experience running tools from Xilinx (ISE, XST) and Lattice (ispLever) on the same Windows computer? I've had problems in the past trying to install Xilinx and Altera (Quartus) on the same machine. In the end I uninstalled the Quartus software and still had to purge my registry of any remnants of it before the Xilinx (Foundation) tools worked again. Right now on one ma...


no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02

Started by ata in comp.arch.fpga13 years ago 2 replies

In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP Starter Kit, the base-system-builder doesn't give me the option of adding the...

In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP Starter Kit, the base-system-builder doesn't give me the option of adding the SystemACE peripheral to the hardware environment. In a text-editor, I manually examined ./board/Xilinx/boards/Xilinx_S3ADSP1800_RevA/data/Xilinx_S3ADSP1800_RevA_v2_2_0.xbd The interface and I/O declarations related to the SystemACE peripheral ar...


FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)

Started by Steven K. Knapp in comp.arch.fpga16 years ago 4 replies

Just FYI, the Spartan-3 XC3S50 through the XC3S1500 FPGAs are all available now via the Xilinx online store at...

Just FYI, the Spartan-3 XC3S50 through the XC3S1500 FPGAs are all available now via the Xilinx online store at ... http://www.xilinx.com/store ... or via the following speedy link. http://tinyurl.com/b6gsn Be sure to click the Refresh button on your browser. Also FYI, the Xilinx Online Store primarily services small-volume or prototyping applications. If your project requires larger ...


Re: Too many signals [Xilinx Foundation 4.1i]

Started by Basuki Endah Priyanto in comp.arch.fpga17 years ago

Hi, many thanks for ur suggestionz, it works !=20 -----Original Message----- From: Colm Clancy [mailto:colmc@xilinx.com] Posted At:...

Hi, many thanks for ur suggestionz, it works !=20 -----Original Message----- From: Colm Clancy [mailto:colmc@xilinx.com] Posted At: Wednesday, December 10, 2003 2:16 AM Posted To: fpga Conversation: Too many signals [Xilinx Foundation 4.1i] Subject: Re: Too many signals [Xilinx Foundation 4.1i] If I remember right this was a known issue way back where the number of = signals on a ...


Xilinx upgrade

Started by Anonymous in comp.arch.fpga13 years ago 4 replies

please i=B4m very new on this, whats the difference between Xilinx ISE and Xilinx=B4s EDK, and what for is the IP ???

please i=B4m very new on this, whats the difference between Xilinx ISE and Xilinx=B4s EDK, and what for is the IP ???


PC configuration for best Xilinx ISE performance

Started by Frai in comp.arch.fpga14 years ago 2 replies

Hello, I want to buy a new PC and I will use it mainly for Xilinx ISE. What is the best configuration? Does Xilinx ISE support Intel Core Duo...

Hello, I want to buy a new PC and I will use it mainly for Xilinx ISE. What is the best configuration? Does Xilinx ISE support Intel Core Duo or AMD Athlon 64 processors? Regards.


Xilinx and archive of Teaching Materials

Started by Pawel Piotr Czapski, SP5EPD in comp.arch.fpga14 years ago

Hi, I'm looking for archive of Teaching Materials (especially, Xilinx FPGA Design Flow Workshop Materials). Those available...

Hi, I'm looking for archive of Teaching Materials (especially, Xilinx FPGA Design Flow Workshop Materials). Those available at http://www.xilinx.com/univ/teaching_material.htm are based on the Xilinx ISE v.8, but I'm interested in these based on v.7. Best regards, Salam mesra, Serdecznie pozdrawiam, Nanyang Technological University, IntelliSys, PhD Student, Pawel Piotr Czapski pczaps...


Does Xilinx have the worst web site on the planet?

Started by Tom Seim in comp.arch.fpga17 years ago 5 replies

Is it me, or do the rest of you have major frustratinos using Xilinx's web site? Just today they had a broken link TO THEIR OWN...

Is it me, or do the rest of you have major frustratinos using Xilinx's web site? Just today they had a broken link TO THEIR OWN SITE!!! Believe me, I have talked to Xilinx managers who have admitted as much.