EDK 7.1 with xilinx ML401 ref design

Started by Antti Lukats in comp.arch.fpga16 years ago 1 reply

Hi I am wondering again and again if xilinx does any testing of the software they release both ISE 7.1 and EDK 7.1 have service paks already...

Hi I am wondering again and again if xilinx does any testing of the software they release both ISE 7.1 and EDK 7.1 have service paks already so I assume some bug tesing and FIXIN has been done? well I am having some trouble with microblaze system that shoud connect to 4 64 bit SDRAM banks using 4 instances of opb2plb bridge. so, problem, oh well lets take a xilinx own KNOWN WORKING DE...


Beginning Xilinx FPGA Tutorials?

Started by Herb T in comp.arch.fpga16 years ago 4 replies

Where to find Tutorials for using Xilinx FPGA? How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? Folks, I am trying to learn...

Where to find Tutorials for using Xilinx FPGA? How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? Folks, I am trying to learn how to program Spartan II (XC2S100-5PQ208C) and Spartan 3 (XC3S400-4PQ208C) Xilinx FPGAs. I looked at the data sheets for these parts, and the more I do the more mystified I get. I have never done this before. I come from a software background, but ha...


Firmware for Xilinx USB cable

Started by rob....@gmail.com in comp.arch.fpga14 years ago 6 replies

Hi, Does anyone have a copy of the latest USB cable firmware version 1025 (the latest according...

Hi, Does anyone have a copy of the latest USB cable firmware version 1025 (the latest according to http://www.xilinx.com/support/programr/usb_history.htm). This file is necessary for use with 2.6 linux kernels and would be in /etc/hotplug/usb/xusbdfwu.fw. The version on the Xilinx website seems to be broken. Xilinx support acknowledge this but are taking some time to get back to me wit...


Bit order reversed in Xilinx post-translate simulation

Started by Jhlw in comp.arch.fpga14 years ago 1 reply

Hi All, Does anyone have any experience with getting their bit order reversed in Xilinx post-translate simulation? I am using Xilinx ISE ver...

Hi All, Does anyone have any experience with getting their bit order reversed in Xilinx post-translate simulation? I am using Xilinx ISE ver 8.2.03i and ModelSim III XE 6.1e starter edition, and this mysteriously started happening to me last week when I never had a problem with this before. I have reinstalled both programs and have reverted to testing only what Xilinx gives me, and I still...


downloading a non-volitle design (xilinx)

Started by GL in comp.arch.fpga17 years ago

How do you download your design (in VHDL) to a Xilinx board and make it non-volitle, using the Xilinx ISE webpack software? Here are the...

How do you download your design (in VHDL) to a Xilinx board and make it non-volitle, using the Xilinx ISE webpack software? Here are the things I've been trying...not yet successful... -generate PROM file -start iMPACT -choose Slave Serial Mode? (I'm confused here...which mode should I choose?) If anyone could tell me the steps, I would really appreciate it. My xilinx board has a SPA...


Xilinx PowerPC & MicroBlaze Development Kit

Started by czeczek in comp.arch.fpga14 years ago 5 replies

Hi, Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze Development Kit in european union ??...

Hi, Is there anyone who knows where can I buy XIlinx PowerPC & MicroBlaze Development Kit in european union ?? (DO-ML403-EDK-ISE, http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS& sSecondaryNavPick=Intellectual+Property&category=&iLanguageID=1&key=DO-ML403-EDK-ISE ) I tried via XIlinx on-line store but since their products are not RoHS compliant


Xilinx self-termination

Started by Antti in comp.arch.fpga13 years ago 3 replies

Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be possible to...

Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be possible to write the GUI that doesnt self-terminate itself so often. I am trying to playback an SVF file, and it caused impact and ISE self- termination. there are possibilites to "CATCH" exceptions and recover the application, but no, Xilinx tools just termi...


Xilinx Spartan-3 Supply Issues?

Started by Gordon in comp.arch.fpga17 years ago 6 replies

Hi all, Hoping for a little bit of insight from all of you: We're currently looking at implementing a small, low-cost PLD implementation on...

Hi all, Hoping for a little bit of insight from all of you: We're currently looking at implementing a small, low-cost PLD implementation on one of our products -- managed Ethernet switch. As Xilinx and Altera are fighting tooth and nail to get in, it's difficult to discern who is telling the truth. The most bothering of all are rumours that Xilinx has yet to perfect the 90um fab, and h...


S3e starter kits available

Started by Alex Gibson in comp.arch.fpga15 years ago 19 replies

According to the front page of xilinx's site but not yet in the web...

According to the front page of xilinx's site but not yet in the web shop. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK With double the amounts of ram and flash than origonally announced. Now if only xilinx sold digilentincs addon cards so could get some decent shipping charges. Alex


How to generate a signal on Xilinx Spartan II

Started by Rakesh Sharma in comp.arch.fpga16 years ago 4 replies

Hi, I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope...

Hi, I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope to hear some noise. My VHDL code, tested on PeakVHDL simulator does generate the waveform and is pasted at the far bottom. The problem is that the code does not compile on Xilinx because "WAIT for 2.5 ns" is not supported on Xilinx Spartan II for...


xilinx free Sample Pack info now also on Xilinx own webpages

Started by Antti Lukats in comp.arch.fpga15 years ago 9 replies

finally the free Sample Pack info is available from Xilinx directly http://www.xilinx.com/products/boards/s3esamplepack/index.htm there is...

finally the free Sample Pack info is available from Xilinx directly http://www.xilinx.com/products/boards/s3esamplepack/index.htm there is no note that there is no availability in Europe so it still makes sense to contact the distributors also in Europe, maybe there is availabily. After one more attempt to use the flashwriter.tcl it worked, so the EDK/XMD/tcl method of programming the o...


Master initialization problem with xilinx 32 bit pci master/target ipcore

Started by chai2m in comp.arch.fpga12 years ago

I am using 32 bit PCI master/target ipcore from Xilinx. Xilinx...

I am using 32 bit PCI master/target ipcore from Xilinx. Xilinx ISE10.1. http://www.xilinx.com/support/documentation/ip_documentation/pci_64_ug159.pdf My problem is, My user application(PCI IP core?s) should be the Master and when it is trying to request the PCI bus, I found a situation that, I have to enable the master bit in Command register(CSR2). I tried the initiator write and sel


some +. for Altera

Started by Antti Lukats in comp.arch.fpga16 years ago 14 replies

Hi first - I am a very Xilinx biased (possible because I have way more Xilinx boards) but the latest Quartus seems really easy and in some...

Hi first - I am a very Xilinx biased (possible because I have way more Xilinx boards) but the latest Quartus seems really easy and in some cases better than X tools (at least the built in programmer is FASTER to use than impact) Story: After getting a nice application tested on Xilinx FPGA I just out of curiosity tried to port to Altera devices, the only problem I had was related to l...


Why is Xilinx's WebPACK so inferior?

Started by Anonymous in comp.arch.fpga14 years ago 50 replies

I've been using the Xilinx Webpack 8.2i since sometime in November, and I've become so irritated with their software that I'm about ready to...

I've been using the Xilinx Webpack 8.2i since sometime in November, and I've become so irritated with their software that I'm about ready to just become a rabid Xilinx basher. I've encountered uncountable crashes while actually trying to use their horribly clunky ISE. On a recent weekend I found four different internal errors in XST while using their command line tools. For a product ...


diff b/w synthesis and implementation in xilinx ISE

Started by vlsi in comp.arch.fpga12 years ago

Hi, What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we...

Hi, What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISE


ASMBL

Started by Shiraz Kaleel in comp.arch.fpga17 years ago 13 replies

While waiting for the next announcement.... perhaps some Xilinx person could answer these questions? Crista Souza's and Ron Wilson's piece in...

While waiting for the next announcement.... perhaps some Xilinx person could answer these questions? Crista Souza's and Ron Wilson's piece in EETimes says in the final paragraph: The column-based approach means that IP companies that either license to Xilinx or want to be acquired will **now have precise physical constraints for how to incorporate their IP into Xilinx FPGAs**. Initial...


PPC on Virtex2P: Jumpstart, recommended reading?

Started by Anonymous in comp.arch.fpga16 years ago 3 replies

Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly paid some dues... I selfishly ask if anyone has compiled a quick set...

Anyone who has used the Power PC cores on Xilinx FPGAs has undoubtedly paid some dues... I selfishly ask if anyone has compiled a quick set of recipes, lessons-learned, or other guides for *quickly* getting up to speed on using these. There is no shortage of documentation available, especially from Xilinx. The problem (in classic Xilinx style) is that I don't have all year to read it. Th...


Very poor Xilinx experience

Started by Simon in comp.arch.fpga9 years ago 10 replies

I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short version: I've bought an...

I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short version: I've bought an SP605 board, it looks as though it's broken - there's no video output from the built-in-self-test program. I have to complete a webcase to get an RMA, and the -ing useless Xilinx mailing-list software won't let me send any inform


Xilinx XC4VSX25 development board?

Started by Peter Moreton in comp.arch.fpga15 years ago 2 replies

Hi, I am looking for an FPGA development board that can host a Xilinx Virtex-4 XC4VSX25 device, because it has 128 multipliers and...

Hi, I am looking for an FPGA development board that can host a Xilinx Virtex-4 XC4VSX25 device, because it has 128 multipliers and is supported by the free Xilinx ISE Webpack edition - however, much Googling has not turned up a board with this device. Can anyone tell me if a development board that hosts the Xilinx 'SX25 exists? - ideally this would have a PCI/PCI-X/PCI-E interface, but ...


Xilinx java application freeze

Started by Sylvain Munaut in comp.arch.fpga15 years ago 5 replies

Hello, I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and I'm having a really big problem. Basically every Xilinx...

Hello, I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and I'm having a really big problem. Basically every Xilinx application based on java (chipscope, planahead, coregen) can just 'freeze' at anytime (usually pretty soon after I launch it). By freeze I mean the GUI completly stops responding and doesn't even refresh anymore. Since the Xilinx tools are more and more based o...