Xilinx Acquires AutoESL

Started by RCIngham in comp.arch.fpga10 years ago 1 reply

Xilinx press release here: http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1521536 Google News results...

Xilinx press release here: http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1521536 Google News results here: http://www.google.co.uk/search?q=Xilinx+Acquires+AutoESL&oi=news_group&ct=title I wonder how many limbs the tool s/w will cost... --------------------------------------- Posted through http://www.FPGARelated.com


Xilinx Conversion 3.1 --> 6.1

Started by Max in comp.arch.fpga16 years ago 5 replies

Hi all, i have an old xilinx project developed with version 3.1 (schematic file) Now i work with Xilinx Project Navigator v.6.1 I'm unable to...

Hi all, i have an old xilinx project developed with version 3.1 (schematic file) Now i work with Xilinx Project Navigator v.6.1 I'm unable to open it. There is any way to convert schematic from 3.1 to 6.1? Thank's in advance Max Udicom


Xilinx Impact order

Started by Brad Smallridge in comp.arch.fpga16 years ago 6 replies

Hello group, I've got 3 Spartans and three platform PROMs in my JTAG daisy chain. Now I can load the first Xilinx fine, but only if I load...

Hello group, I've got 3 Spartans and three platform PROMs in my JTAG daisy chain. Now I can load the first Xilinx fine, but only if I load it first. If I load the second Xilinx and then try to load the first, the Done pin won't go high. Any suggestions? Brad Smallridge


New Home

Started by austin in comp.arch.fpga13 years ago 3 replies

Hi, Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx). The bad news(?): I will still...

Hi, Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx). The bad news(?): I will still participate here on c.a.f. and my Xilinx blog (is that of any use to anyone?) and I am still willing to find the answers to those questions that seem not to have any answers in our documentation, or on our website. The good news(?): I no longer manage the...


Free alternatives to Xilinx iMPACT?

Started by Philipp Klaus Krause in comp.arch.fpga7 years ago 6 replies

I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to program CPLDs. Is there a free alternative (preferably some...

I have a Xilinx Platform Cable USB. With Xilinx iMPACT I can use it to program CPLDs. Is there a free alternative (preferably some command-line tool that works on Linux)? Philipp


Xilinx CoreGen fifo - ngdbuild error

Started by Markus Fras in comp.arch.fpga14 years ago 3 replies

Hi everybody, since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and Xilinx ISE 9.1. I have...

Hi everybody, since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and Xilinx ISE 9.1. I have a fifo IP generated the Xilinx CORE Generator. In my design, I make an instance of the fifo and can simulate it. For precision, I added two lines to the compilation script: add_input_file fifo18w16d.v add_input_file -exclude fifo18w16d.edn ...


problems with Xilinx GSRD design for ML403

Started by leevv in comp.arch.fpga16 years ago

Hi All I just tried GSRD design for ML403 from Xilinx web site Did smbd in Xilinx make final test at all I'm using ISE7.1sp2 and...

Hi All I just tried GSRD design for ML403 from Xilinx web site Did smbd in Xilinx make final test at all I'm using ISE7.1sp2 and EDK7.1sp1 Bit file compiles fine When I tried to start XMD from XPS environment, program didn't start (I tried supplied downloads elf files also). After several hours o attempts I tried to start Xilinx Shell first and then typed XMD Magic - it works Next story...


Xilinx IOSTANDARD for PCI-X 100MHz interface

Started by Nahum Barnea in comp.arch.fpga17 years ago 5 replies

Hi. I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. What IOSTANDARD should I use in the .ucf file ? I see...

Hi. I am designing PCI-X interface on Xilinx virtex2 pro with 100 MHz frequency. What IOSTANDARD should I use in the .ucf file ? I see only PCI33_3 and PCI66_3 in Xilinx litrature as "PCI" I/O's. ThankX NAHUM


Xilinx HW-SPAR3_CPLD-DK kit

Started by Apostol in comp.arch.fpga15 years ago 1 reply

Please let me know any Xilinx distributor from any European Union country in order to by the HW-SPAR3_CPLD-DK kit. Xilinx price is $99 but if...

Please let me know any Xilinx distributor from any European Union country in order to by the HW-SPAR3_CPLD-DK kit. Xilinx price is $99 but if Imported from USA including Shipping and Taxes the final price is near $200


PCI Parallel port detection in XILINX

Started by Aditi in comp.arch.fpga10 years ago 7 replies

Hi, I have installed a PCI parallel port card on my PC. And I want to run XILINX and let it detect the card so that I can use a XILINX...

Hi, I have installed a PCI parallel port card on my PC. And I want to run XILINX and let it detect the card so that I can use a XILINX Parallel Cable IV to work with it. XILINX detects the card but gives an error message saying "ECP port test failed." and does not work. How do I get the PCI parallel card to work with XILINX? Is there a particular PCI card which someone has worked with...


XILINX

Started by FPGAGUYJR in comp.arch.fpga17 years ago

Please feel free to contact me regarding any of your FPGA/Xilinx needs, especially with those parts that have long lead times. We are one of...

Please feel free to contact me regarding any of your FPGA/Xilinx needs, especially with those parts that have long lead times. We are one of the largest stocking Xilinx distributors, with pricing below market costs. We are ISO 9002:2000 CERTIFIED. All parts are new, unused, and have the manufacturer guarantee. Let me know if you have any questions. www.sgidirect.com We specialize in...


Xilinx news

Started by John Larkin in comp.arch.fpga10 years ago 52 replies

http://www.eetimes.com/electronics-news/4212400/Xilinx-to-shutter-French-R-D-operation Yikes, this explains some stuff. I wonder how long it...

http://www.eetimes.com/electronics-news/4212400/Xilinx-to-shutter-French-R-D-operation Yikes, this explains some stuff. I wonder how long it will take to undo the damage. Our latest projects are using Altera parts, purely because the Xilinx software is such a train wreck. John


newbie - TCP/IP

Started by ram in comp.arch.fpga17 years ago 1 reply

Hi Group, I need help on using the XilNet libraray and Xilinx EMAC core. ( www.xilinx.com) I am a newbie to TCP/IP stack , so I need some...

Hi Group, I need help on using the XilNet libraray and Xilinx EMAC core. ( www.xilinx.com) I am a newbie to TCP/IP stack , so I need some pointers on where to get started. I have seen Xilinx App notes , but the C files are too confusing for me, and it has plethora of socket functions,. Can anybody please point me how to get started and going. I appreciate your help in advance Thank you ...


agen Xilinx di Indonesia

Started by Anonymous in comp.arch.fpga13 years ago

PT Nesyer Electronic, agen resmi produk Xilinx dan bnayk merk semiconductor yang lain, www.nesyer.com, official representative office of...

PT Nesyer Electronic, agen resmi produk Xilinx dan bnayk merk semiconductor yang lain, www.nesyer.com, official representative office of Avnet Inc, Xilinx authorized distributor


Is the Xilinx's silicon better than Altera's?

Started by Bruce Sam in comp.arch.fpga16 years ago 3 replies

I have never used Xilinx's product before.In some articles are said the Xilinx's silicon is better than Altera.Is it realy?I'm only a university...

I have never used Xilinx's product before.In some articles are said the Xilinx's silicon is better than Altera.Is it realy?I'm only a university student and not have enough money to validate it.Can give some advice to me?


LFSR in xilinx 13.2

Started by salimbaba in comp.arch.fpga9 years ago 4 replies

Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core gen. I am using Spartan3...

Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000 FPGA. Does anyone know where i can find it? regards --------------------------------------- Posted through http://www.FPGARelated.com


Xilinx-gdb Sources publicly available?

Started by Mario Trams in comp.arch.fpga17 years ago 6 replies

Dear fellows, according http://www.xilinx.com/ise/embedded/gdb_debugger.htm Xilinx has slightly modified the gdb used for debugging of the...

Dear fellows, according http://www.xilinx.com/ise/embedded/gdb_debugger.htm Xilinx has slightly modified the gdb used for debugging of the VirtexIIPro PPC405. Doeas anybody know whether there are Sources or at least patches of/for this gdb laying around somewhere? I couldn't find anything so far and I guess that they are not publicly available. Actually, I would like to use the ...


Xilinx ISE 6.2i WebPack & project restoration

Started by Christian E. Boehme in comp.arch.fpga16 years ago 2 replies

Hi all, I am currently using the (gratis) Xilinx ISE 6.2i WebPack for Windows version for developing CPLD and FPGA designs for reasons that...

Hi all, I am currently using the (gratis) Xilinx ISE 6.2i WebPack for Windows version for developing CPLD and FPGA designs for reasons that shall not be discussed right now ;) First thought was to play a little with the tools that come with it using some application notes code from Xilinx (namely from XAPP137). Well, that first attempt half-way failed due to the fact that I somehow seeme...


Problema when upgrading from Xilinx 8.1 to Xilinx 8.2

Started by Zara in comp.arch.fpga14 years ago 12 replies

This is not strictly a call for help, it is more of a warning to everyone. Yesterday, I tried to upgrade from ISE/EDK 8.1 to ISE/EDK 8.2,...

This is not strictly a call for help, it is more of a warning to everyone. Yesterday, I tried to upgrade from ISE/EDK 8.1 to ISE/EDK 8.2, and also change from Xilinx Paralllel IV (it always worked as PC III) to USB Platform cable Steps: 1) Uninstall all older versions. Easy, it works nice. 2) Install ISE 8.2 and all upgrades/sp's. Slow (lots of mb), but it works. 3) Import old C...


counterfeit Xilinx ?

Started by Jon Elson in comp.arch.fpga13 years ago 35 replies

I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese seller, and am having problems with random failures at first power up. Sometimes...

I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese seller, and am having problems with random failures at first power up. Sometimes it is a stuck I/O pin, sometimes a failure to configure. I first thought maybe we had an ESD problem, but I'm now thinking these may be counterfeit. They have white ink printed labels on the front, whereas other Xilinx chips have laser-etched l...