I haven't used picoblaze, so take my comment accordingly:  If picoblaze is placed in the source code using generates, it may not be
possible to do it in verilog and retain the placement as well as the parameterization.  If using synplify, you can compile the VHDL with
the mapped output to verilog turned on to get a structural verilog model that you can use for simulation.  Be aware that SRL16's may not
be initialized properly though (I don't know if Synplicity fixed that bug in 7.5.1).

Allan Herriman wrote:

> On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
> wrote:
>
> >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
> >> This doesn't help the OP though, as the core itself is written in
> >> VHDL.  Steve, would there be any problem if a third party (e.g. me)
> >> were to publish a behavioural Verilog description of picoblaze[123]?
> >
> >Allan:
> >The Picoblaze cores are, although VHDL, just instantiations of LUTS
> >and FF's. So a straight translation should be possible.
>
> Possible, yes, but would it be frowned upon by Xilinx?
>
> Regards,
> Allan.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Allan Herriman wrote:

> On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
> wrote:
> 
>>Allan:
>>The Picoblaze cores are, although VHDL, just instantiations of LUTS
>>and FF's. So a straight translation should be possible.
> 
> 
> Possible, yes, but would it be frowned upon by Xilinx?


I am not the official word of Xilinx but if you are buying Xilinx 
devices to use that code in, I doubt you will have a problem with this. 
   If you are trying to re-target this code to another vendor's FPGA, 
then you might.  The code was written to sell Xilinx FPGAs and as long 
as it does that in either VHDL or Verilog form, then I would not worry 
to much about the translation.  My suggestion however is to just 
synthesize your design with the processor defined as a black-box in you 
Verilog code and use the provided NGC file.  If you want to run a 
behavioral Verilog sim using it, then you can translate the NGC file to 
a structural UNISIM-based model using NGC2HDL.  Since it sounds like the 
original is structural, this should be practically the same thing as the 
VHDL version.  I would not suggest implementing the Verilog file 
produced by NGC2HDL however as it is only really intended to be used for 
simulation so I would stick with the original NGC file for 
implementation to be safe.

-- Brian


> 
> Regards,
> Allan.

On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
wrote:

>Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
>> This doesn't help the OP though, as the core itself is written in
>> VHDL.  Steve, would there be any problem if a third party (e.g. me)
>> were to publish a behavioural Verilog description of picoblaze[123]?
>
>Allan:
>The Picoblaze cores are, although VHDL, just instantiations of LUTS
>and FF's. So a straight translation should be possible.

Possible, yes, but would it be frowned upon by Xilinx?

Regards,
Allan.

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
> This doesn't help the OP though, as the core itself is written in
> VHDL.  Steve, would there be any problem if a third party (e.g. me)
> were to publish a behavioural Verilog description of picoblaze[123]?

Allan:
The Picoblaze cores are, although VHDL, just instantiations of LUTS
and FF's. So a straight translation should be possible.
Henk

On 18 Jun 2004 02:43:41 -0700, henk@mediatronix.com (Henk van Kampen)
wrote:

>Dear Steve/Allan:
>What would be needed in my Picoblaze IDE to support Verilog. Please
>let me know, so when I find the time I can add that.

Hi Henk, it just needs to be able to generate the file containing the
ROM contents in Verilog instead of VHDL.
Kcpsm3 generates files in both languages, perhaps you could study what
it does.

This doesn't help the OP though, as the core itself is written in
VHDL.  Steve, would there be any problem if a third party (e.g. me)
were to publish a behavioural Verilog description of picoblaze[123]?

Regards,
Allan.

Dear Steve/Allan:
What would be needed in my Picoblaze IDE to support Verilog. Please
let me know, so when I find the time I can add that.

Regards,
Henk van Kampen

On Thu, 17 Jun 2004 16:29:49 -0700, "Steven K. Knapp"
<steve.knappNO#SPAM@xilinx.com> wrote:

>
>"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
>message news:drb3d09tn390n8g3m7a0fdebqqapvc20r9@4ax.com...
>
>> [Allan calls it a bug]
>> 
>
> [Steve calls it a feature]

That's pretty much the response I expected.

Regards,
Allan.

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:drb3d09tn390n8g3m7a0fdebqqapvc20r9@4ax.com...

[snip]

> Some bugs in kcpsm2.exe are also present in kcpsm3.exe (see webcases
> #533179 and #533195).


It appears that web case #533195 relates to the DOS 8.3 filename
requirements for the KCPSM3 assembler.  This is an unfortunate side effect
of maintaining compatibility with the widest number of development computers
and with the original choice of programming languages to create the KCPSM3
assember.

One alternative is to use the more modern Mediatronix pBlazIDE graphical
development environment, which is also no charge.  The instruction nmemonics
are slightly different than the KCPSM3 assembler but the pBlazIDE software
has a code import function that reads KCPSM3 code.  Furthermore, the
pBlazIDE software includes an instruction-set simulator.
http://www.mediatronix.com/pBlazeIDE.htm

> Kcpsm3.exe can't compile code that compiles with kcpsm2.exe.  (This
> violates one of the cardinal rules of EDA - don't break existing
> designs.)
> The problem seems to be that kcpsm3 doesn't accept register names of
> the form 's00', which is the only form that kcpsm2 accepts.

There are some differences between the PicoBlaze controller for the
Spartan-3, Virtex-II, and Virtex-II Pro FPGA families and the older version
available for just Virtex-II and Virtex-II Pro.  The latest incarnation
includes two new instructions (COMPARE, TEST) plus a 64-byte scratchpad RAM,
although the number of registers dropped back to 16 from 32.

You can use the NAMEREG assembler directive to handle the different register
assignment.  Here's an example.  Just add the following code to the start of
your

NAMEREG s0, s00    ; alias old register name s00 to s0
NAMEREG s1, s01    ; alias old register name s01 to s1
...
NAMEREG sF, s0F    ; alias old register name s0F to sF

Then the remainder of your code should compile using the old names.
However, you still need to adjust the register assignments for the upper 16
registers.

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

On Thu, 17 Jun 2004 07:29:26 -0700, Shalin Sheth
<Shalin.Sheth@xilinx.com> wrote:

>Allan,
>
>To register and download Picoblaze3:
>- Goto http://www.xilinx.com/picoblaze
>- Click on 'PicoBlaze for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs'
>- Click on the 'Download' button
>- Click on 'Create an Account' button

got it, thanks.

First impressions:

Picoblaze3 has 16 registers vs 32 for Picoblaze2.

Some bugs in kcpsm2.exe are also present in kcpsm3.exe (see webcases
#533179 and #533195).

Kcpsm3.exe can't compile code that compiles with kcpsm2.exe.  (This
violates one of the cardinal rules of EDA - don't break existing
designs.)
The problem seems to be that kcpsm3 doesn't accept register names of
the form 's00', which is the only form that kcpsm2 accepts.

Regards,
Allan.

Allan,

To register and download Picoblaze3:
- Goto http://www.xilinx.com/picoblaze
- Click on 'PicoBlaze for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs'
- Click on the 'Download' button
- Click on 'Create an Account' button

Cheers,
Shalin-

Allan Herriman wrote:
> On Thu, 17 Jun 2004 10:18:38 -0300, "INS122595"
> <walter@chasque.apc.org> wrote:
> 
> 
>>Check the latest version KCPSM3, I don't use Verilog but the assembler have
>>a Verilog rom form.
> 
> 
> Hi Walter, do you know where I can download KCPSM3?  The Xilinx site
> requires a user name and password, but I can't find a page that will
> allow me to register (again).
> 
> Regards,
> Allan.