GaborSzakacs wrote:
> VHDL for everything?  Even the memory models?  I haven't seen any
> DDR2 memory models in VHDL.  That would make you need a mixed
> language simulator license even if the full controller model
> was in VHDL.
Back then I used Samsung chips, and they provided precompiled (ModelSim)
models for one of their DRAM chips (luckily, the one I was using, or one
close enough). They even recompiled for me since I was using a newer
ModelSim release than the one they had models for and the "refresh"
option didn't work.

<rant>
But that was the one and only time I had Samsung do anything good for
me. They proved uncooperative in absolutely every aspect before and
after that, so I've banned everything Samsung from all my designs for
the past 10 years (and convinced most of my colleagues to do the same).
Another one of those companies that just don't care if you buy less than
a million units a year...
</rant>

For my current design, I fortunately have a dual-language simulator
license, so that's not an issue.

Greetings,
Sean

On 22/05/2013 19:51, GaborSzakacs wrote:
> Sean Durkin wrote:
>> Hi Bodo,
>>
>> Bodo wrote:
>>> Hello,
>>> I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I
>>> have some "problems"
>>> during generation of the simulation models from the MIG-tool. Only the
>>> top-level of the DDR2-memory-controller
>>> is generated in VHDL, the instantiated moduls are generated in Verilog.
>>> This is a problem, because I don't have a mixed-language simulator.
>>> Are there any experiences using the DDR2-controller of the new 7-series
>>> from XILINX?
>>
>> I'm currently doing a DDR3-design for Artix-7. The controller code
>> itself is also always provided as Verilog, only the top level is VHDL.
>> Besides, when using Vivado, the entire process of generating an example
>> design is broken when you select VHDL for generation.
>>
>> To me it seems like the guy(s) doing the controller design is/are
>> working with Verilog only.
>> Kind of makes sense not to develop versions in two languages in
>> parallel, but it used to be different... I did a DDR2-design on Virtex-4
>> with an older release of MIG (I believe it was 1.2 or so), and they
>> provided VHDL-code for everything back then (which was good since it
>> needed to be modified quite heavily).
>>
>
> VHDL for everything?

Yes, I believe that most DDRx memory controllers (and other hard-ip) are 
written in encrypted (System)Verilog which a VHDL user could use using 
the SecureIP (Modelsim and Aldec?) license feature. I suspect that with 
their own "dual language out of the box ISIM simulator" Xilinx might 
have forgotten the other simulator users.

Even the memory models?

Yes, VHDL DDRx memory models are available from Hynix and RASSP. 
Unfortunately AFAIK most companies tend to use Micron which are all in 
Verilog. A friend of mine who works for a big avionics company asked 
Micron to provide some VHDL models but they never came back to him (no 
surprise I guess). It is not that expensive for a company the size of 
Micron to provide models in all 3 RTL languages. So perhaps now is a 
good time to promote Hynix memory models, they are twice as succulent...

I haven't seen any
> DDR2 memory models in VHDL.
That would make you need a mixed
> language simulator license even if the full controller model
> was in VHDL.
>
>> The only thign you could do is uses Xilinx' simulation tool, that comes
>> with mixed-language support by default.

Or complain to your simulator vendor that in 2013 simulators should be 
dual language out of the box for exactly this reason. All synthesis 
tools are now dual language so why not simulators.

Hans
www.ht-lab.com


>>
>> Greetings,
>> Sean
>

Sean Durkin wrote:
> Hi Bodo,
> 
> Bodo wrote:
>> Hello,
>> I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I
>> have some "problems"
>> during generation of the simulation models from the MIG-tool. Only the
>> top-level of the DDR2-memory-controller
>> is generated in VHDL, the instantiated moduls are generated in Verilog.
>> This is a problem, because I don't have a mixed-language simulator.
>> Are there any experiences using the DDR2-controller of the new 7-series
>> from XILINX?
> 
> I'm currently doing a DDR3-design for Artix-7. The controller code
> itself is also always provided as Verilog, only the top level is VHDL.
> Besides, when using Vivado, the entire process of generating an example
> design is broken when you select VHDL for generation.
> 
> To me it seems like the guy(s) doing the controller design is/are
> working with Verilog only.
> Kind of makes sense not to develop versions in two languages in
> parallel, but it used to be different... I did a DDR2-design on Virtex-4
> with an older release of MIG (I believe it was 1.2 or so), and they
> provided VHDL-code for everything back then (which was good since it
> needed to be modified quite heavily).
> 

VHDL for everything?  Even the memory models?  I haven't seen any
DDR2 memory models in VHDL.  That would make you need a mixed
language simulator license even if the full controller model
was in VHDL.

> The only thign you could do is uses Xilinx' simulation tool, that comes
> with mixed-language support by default.
> 
> Greetings,
> Sean

-- 
Gabor

Hi Bodo,

Bodo wrote:
> Hello,
> I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I
> have some "problems"
> during generation of the simulation models from the MIG-tool. Only the
> top-level of the DDR2-memory-controller
> is generated in VHDL, the instantiated moduls are generated in Verilog.
> This is a problem, because I don't have a mixed-language simulator.
> Are there any experiences using the DDR2-controller of the new 7-series
> from XILINX?

I'm currently doing a DDR3-design for Artix-7. The controller code
itself is also always provided as Verilog, only the top level is VHDL.
Besides, when using Vivado, the entire process of generating an example
design is broken when you select VHDL for generation.

To me it seems like the guy(s) doing the controller design is/are
working with Verilog only.
Kind of makes sense not to develop versions in two languages in
parallel, but it used to be different... I did a DDR2-design on Virtex-4
with an older release of MIG (I believe it was 1.2 or so), and they
provided VHDL-code for everything back then (which was good since it
needed to be modified quite heavily).

The only thign you could do is uses Xilinx' simulation tool, that comes
with mixed-language support by default.

Greetings,
Sean

>Hello,
>I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I 
>have some "problems"
>during generation of the simulation models from the MIG-tool. Only the 
>top-level of the DDR2-memory-controller
>is generated in VHDL, the instantiated moduls are generated in Verilog.
>This is a problem, because I don't have a mixed-language simulator.
>Are there any experiences using the DDR2-controller of the new 7-series
from 
>XILINX?
>Thank you,
>Bodo 
>

I had some experience with Virtex-4 and V5 DDR2 Controllers some time ago.

The underlying logic was generated in VHDL, but the Micron DDR2 models were
only available in Verilog.
Fortunately, we had some mixed-language licences.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hello,
I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I 
have some "problems"
during generation of the simulation models from the MIG-tool. Only the 
top-level of the DDR2-memory-controller
is generated in VHDL, the instantiated moduls are generated in Verilog.
This is a problem, because I don't have a mixed-language simulator.
Are there any experiences using the DDR2-controller of the new 7-series from 
XILINX?
Thank you,
Bodo