Reply by guhaoqi July 9, 20042004-07-09
try
Reply by Rakesh YC July 9, 20042004-07-09
Hi all

My problem is I'd like to choose a VHDL file instantiated inside
verilog via VHDL
configuration

To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl:
bottom" How to write a vhdl configuration to select the file for the
bottom instantiation?

Rakesh YC