Reply by Martin Schoeberl●February 21, 20052005-02-21
> VHDL level simulation of JOP is now available ;-)
>
> The actual version of JOP at the usual download page
> http://www.jopdesign.com/download.jsp
> now contains (hopefully) all necessary file to run a
> simulation with ModelSim or a different VHDL
> simulator.
>
> A (very) simple step-by-step introduction can be found at:
> http://www.jopdesign.com/simulation.jsp
>
I've added a simulation version of the uart module (sim_uart.vhd)
to speed-up the simulation a little bit. It's too monotonous to watch
the simulation generating the output at 115kbaud ;-)
Martin
Reply by Martin Schoeberl●February 20, 20052005-02-20
VHDL level simulation of JOP is now available ;-)
The actual version of JOP at the usual download page
http://www.jopdesign.com/download.jsp
now contains (hopefully) all necessary file to run a
simulation with ModelSim or a different VHDL
simulator.
In directory vhdl/simulation you will find:
* A test bench: tb_jop.vhd with a serial receiver to print out
the messages from JOP during the simulation
* Simulation versions of all memory components (vendor neutral)
* Simulation of the main memory
In directory modelsim you will find a small batch file (sim.bat) that compiles
JOP and the test bench in the correct order and starts ModelSim.
A (very) simple step-by-step introduction can be found at:
http://www.jopdesign.com/simulation.jsp
It would be nice if somebody can try the simulation to check whether all scripts
and directories are correctly set.
Cheers and thanks for checking it out ;-),
Martin
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JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/