> > > There are two ways to synthesize a memory in an FPGA. One is to use
> > > verilog's reg as you suggested, the other one is to use Vendor
> Specific
> > > Primitive. Using verilog's reg is the most portable one. It works
> with
> > > all FPGAs with little or no modification. But it takes valuable
> space
> > > in your FPGA logic that otherwise can be used for other purposes.
> >
> > Most of the synthesis tools are able to infer dedicated RAM blocks.
>
> With XST, how do I know that my code is synthesized to a RAM made from
> the logic, or RAM made from the dedicated RAM blocks?

The synthesis report will tell you if the tool inferred RAM.

Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

Jim Wu wrote:
> "Hendra" <u1000393@email.sjsu.edu> wrote in message
> > There are two ways to synthesize a memory in an FPGA. One is to use
> > verilog's reg as you suggested, the other one is to use Vendor
Specific
> > Primitive. Using verilog's reg is the most portable one. It works
with
> > all FPGAs with little or no modification. But it takes valuable
space
> > in your FPGA logic that otherwise can be used for other purposes.
>
> Most of the synthesis tools are able to infer dedicated RAM blocks.

With XST, how do I know that my code is synthesized to a RAM made from
the logic, or RAM made from the dedicated RAM blocks?

Hendra

"Hendra" <u1000393@email.sjsu.edu> wrote in message
news:1112055725.715876.230210@l41g2000cwc.googlegroups.com...
> paulw@mmail.ath.cx wrote:
> > Is it a good idea to use verilog's reg to declare a large block of
> > memory and expect it will be synthesizable?
>
> There are two ways to synthesize a memory in an FPGA. One is to use
> verilog's reg as you suggested, the other one is to use Vendor Specific
> Primitive. Using verilog's reg is the most portable one. It works with
> all FPGAs with little or no modification. But it takes valuable space
> in your FPGA logic that otherwise can be used for other purposes.

Most of the synthesis tools are able to infer dedicated RAM blocks.

Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


An
> alternative way is to instantiate Vendor Specific Primitive. This
> method is not portable. You must instantiate different primitive for
> different chips family and vendors. However, you will safe a lot of
> space in your chips since instantiating a Vendor Specific Primitive
> means you will use a dedicated memory in the chip, leaving the logic
> free to be used for other purposes.
>
> Hendra
>

paulw@mmail.ath.cx wrote:
> Is it a good idea to use verilog's reg to declare a large block of
> memory and expect it will be synthesizable?

There are two ways to synthesize a memory in an FPGA. One is to use
verilog's reg as you suggested, the other one is to use Vendor Specific
Primitive. Using verilog's reg is the most portable one. It works with
all FPGAs with little or no modification. But it takes valuable space
in your FPGA logic that otherwise can be used for other purposes. An
alternative way is to instantiate Vendor Specific Primitive. This
method is not portable. You must instantiate different primitive for
different chips family and vendors. However, you will safe a lot of
space in your chips since instantiating a Vendor Specific Primitive
means you will use a dedicated memory in the chip, leaving the logic
free to be used for other purposes.

Hendra

paulw@mmail.ath.cx wrote:
> Hi
> 
> Someone must have ask this question before. Is it a good idea to use
> verilog's reg
> to declare a large block of memory and expect it will be synthesizable?
> 
> 
> Thanks
> 
Most synthesizers will infer such a block as FPGA block memory if the 
HDL is written in a certain way.  Look at the user's guide of your 
synthesizer for more details.
-Kevin

Hi

Someone must have ask this question before. Is it a good idea to use
verilog's reg
to declare a large block of memory and expect it will be synthesizable?


Thanks