Reply by May 22, 20182018-05-22
On Saturday, April 14, 2018 at 11:06:42 AM UTC-4, Piotr Wyderski wrote:
> I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but > a showstopper for hobby applications, where you can buy a bucket > of STM32-class chips. > > 2. The chip must be hand-solderable and introduce no thermal strain > problems. This excludes the BGA/chip scale packages and leaves only > the QFP variants on the table. I don't care about the superior > signal integrity benefits of the leadless packages, 50MHz is more > than needed. But this requirement kills Zynq/Cyclone V, otherwise > a perfect choice for this application. The PCB must be manufacturable > in a cheap PCB shop and they can often do at most 4 layers. > > 3. The FPGA must be SRAM-based. > > 4. I don't want the SOM modules. > > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > would have been aa good choice here, but I seem to be blocked by > the licenseing issues. I'd gladly stick to these platforms, but > could you please recommend me any robust open-source IP cores > which fit inside this class of FPGAs?
I read much of the thread but not all. I don't think I have anything meaningful to add to the discussion as asked by the OP. I do feel his pain about the available packages for FPGAs. My desire is to have FPGA devices that are similar in package and utility to smaller MCUs including price competitiveness. I don't care about hand soldering since that is of no economic value and I am in business. My interest in using leaded or no-lead devices rather than BGA type packages is convenience and the cost of PWBs. While the larger BGAs often have wider pin pitches and so are not difficult to route with relaxed design rules, they are big and expensive mitigating the point of using low cost PWBs. Smaller pin count packages at a lower unit price use much finer ball pitches and require the most expensive PWB processing. As a result there are no $10 FPGA boards available much less $5 FPGA boards even though there are a number of FPGAs well below this price. I recall having conversations here with Xilinx representatives about the cost basis for FPGAs and often the die size was pin count limited. So the smallest devices were fairly large by some standards. Lattice is the only FPGA company I am aware of that makes devices that only have a couple dozen I/Os or less across all packages. Because of the market for these devices they end up in microscopic packages that are not practical for low cost production unless very high volumes are produced. Rick C.
Reply by Theo April 18, 20182018-04-18
DJ Delorie <dj@delorie.com> wrote:
> > Theo Markettos <theom+news@chiark.greenend.org.uk> writes: > >> I've got a virtex-7 board running Fedora on a quad-core 64-bit RISC-V. > >> Is that big enough? ;-) > > > > Which core are you using? > > It's the sifive freedom unleashed core, the U500.
So that's based on Rocket. Thus far I only know about Rocket and PULP's Ariane that are able to boot Linux.
> > I don't think the V7 comes in QFP ;-) > > Nope.
Shucks :) Might be over the OP's budget anyway... by a factor of 100. Theo
Reply by DJ Delorie April 18, 20182018-04-18
Theo Markettos <theom+news@chiark.greenend.org.uk> writes:
>> I've got a virtex-7 board running Fedora on a quad-core 64-bit RISC-V. >> Is that big enough? ;-) > > Which core are you using?
It's the sifive freedom unleashed core, the U500.
> I don't think the V7 comes in QFP ;-)
Nope.
Reply by Theo Markettos April 17, 20182018-04-17
DJ Delorie <dj@delorie.com> wrote:
> > Theo Markettos <theom+news@chiark.greenend.org.uk> writes: > > Do you know of any RISC-V cores on FPGA which are capable of booting Linux? > > I've got a virtex-7 board running Fedora on a quad-core 64-bit RISC-V. > Is that big enough? ;-)
Which core are you using? I don't think the V7 comes in QFP ;-) Theo
Reply by DJ Delorie April 17, 20182018-04-17
Theo Markettos <theom+news@chiark.greenend.org.uk> writes:
> Do you know of any RISC-V cores on FPGA which are capable of booting Linux?
I've got a virtex-7 board running Fedora on a quad-core 64-bit RISC-V. Is that big enough? ;-)
Reply by Theo Markettos April 17, 20182018-04-17
Anssi Saari <as@sci.fi> wrote:
> For a soft CPU a RISC-V might be reasonable and a Linux port exists even > if it's very new. RISC-V is an instruction set but as I understand it, > there are loads of free implementations on Github.
Do you know of any RISC-V cores on FPGA which are capable of booting Linux? There's loads of microcontroller-class cores, but not many larger ones. I've only seen Rocket, which is somewhat awkward to deal with, and LowRISC which is an older version of Rocket (those folks are at the forefront of suffering the pain of interfacing with Rocket). SiFive are shipping(ish) silicon with Rocket in it. There's also PULP and various CPUs from IIT Madras, but I'm not sure what state of completeness they're in. In our experience with BERI (which is a 100MHz 64 bit CPU with caches and MMU, but using the MIPS ISA and runs FreeBSD rather than Linux), it'll fit on a 115K Cyclone IV but nothing much smaller. Theo
Reply by Robert Swindells April 17, 20182018-04-17
On Sat, 14 Apr 2018 17:06:37 +0200, Piotr Wyderski wrote:

> I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but a > showstopper for hobby applications, where you can buy a bucket of > STM32-class chips.
Have you looked at the LM32 CPU core ?
Reply by Anssi Saari April 17, 20182018-04-17
Piotr Wyderski <peter.pan@neverland.mil> writes:

> I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but:
I think Lattice has the IP available for free. But no solderable FPGAs in the relevant families it seems. The other small player, Microsemi (or Microchip now) almost seems to have the FPGAs in the Igloo2 family, TQFP package with 84 I/O and a hard DDR2/DDR3 controller but I don't know about free IP. Or if the chips that are available in the TQFP are big enough for this (12k LEs, I think Altera's Max10 demo boards stuffed a Nios in their 8 k LE devices). Looks like Intel's Max 10 is the best bet for FPGA. EQFP package with 101 I/O and hard DDR2/3.
> Are there any *reasonable* open CPU/MAC/memory controller cores to use > instead?
For a soft CPU a RISC-V might be reasonable and a Linux port exists even if it's very new. RISC-V is an instruction set but as I understand it, there are loads of free implementations on Github. I don't know if decent ethernet MACs with Linux drivers are available for free. Maybe consider a separate chip? Microchip's ENC28J60 is probably one of the cheapest but it's 10 Mbps and SPI interface.
Reply by David Brown April 16, 20182018-04-16
On 15/04/18 20:40, Joe Chisolm wrote:

> I think it's a noble cause and I'd love to see more people know > the down and dirty of how a box works but what you are asking is > indeed difficult. If your hobbist target group is people doing > digital design, maybe a uC with glue logic, etc is one thing but > taking some person who's been doing python on linux and get them > thinking hardware, VHDL or Verilog thinking, can be a rather large > mountian to climb. > >
That immediately brings to mind MyHDL - do the HDL design in Python. Putting a big cpu and logic for a Linux system in an FPGA is a complex task - even with a hard cpu core. I can't see how it adds anything to a "learn hardware design" board. I am not even convinced that a microcontroller beside the FPGA is worth the effort, but it could be fun to play with. Key features I would think for the system are: 1. An FPGA with some pins on LEDs, keys, etc., and some on headers. 2. An Arduino ARM compatible microcontroller and layout, with some pins on LEDs, keys, etc., and some to the FPGA. 3. A USB hub chip, with downstream components (FTDI devices or whatever) covering an FPGA interface compatible with a standard programmer for the FPGA device, a programmer interface for the Arduino chip, a serial port, and a connection to the FPGA for making your own USB device in programmable logic. 4. A few sensors, buzzers, etc. 5. Arduino compatible or Raspberry Pi compatible headers, but connected to the FPGA pins. And on the software side, a whole bunch of MyHDL examples and components for the board. Plus some in VHDL and some in Verilog, for more advanced stages.
Reply by Theo Markettos April 15, 20182018-04-15
Joe Chisolm <jchisolm6@earthlink.net> wrote:
> I think it's a noble cause and I'd love to see more people know > the down and dirty of how a box works but what you are asking is > indeed difficult. If your hobbist target group is people doing > digital design, maybe a uC with glue logic, etc is one thing but > taking some person who's been doing python on linux and get them > thinking hardware, VHDL or Verilog thinking, can be a rather large > mountian to climb.
Agreed 110%. What's more, a lot of this is out of the competence of people who do software. There's a huge pile of stuff built just to get to a shell prompt. But maybe your thing doesn't work. Is it a software bug, an OS bug, a compiler bug, a cache bug, a CPU bug, a peripheral bug, a memory bug, it failed to meet timing, you failed to constrain it properly, a signal integrity bug, a power supply bug...? The reason I suggested looking again at systems-on-module, particularly the ones with hard ARM cores in them, is that you have at least a working system that will reliably boot Linux, without too much in the way of dependencies on external infrastructure - just power and connectors. The OS works, the compiler is fairly well tested, the dev environment is familiar and tools like gdb work. All of these you have to build yourself from the ground up with a soft CPU. Then, if you wish, you can build your own CPU alongside in the FPGA soft-logic. Eventually you can turn off the ARM altogether if you want. But you always have the ARM as a familiar dependable environment to fall back on as a halfway house - and to debug your soft CPU. SOMs make custom PCB assembly easier, but also people can use off-the-shelf dev boards if they want. The only thing you lose is the ability to solder your own FPGA, which is not really an advantage to anyone unless you're selling in volume. Oh, did I also mention it's hard to buy FPGAs for sane prices if you're not selling in volume? Theo