Hey,

I just got a board with a virtex4 and there is a LVDS connection on it and
another LVDS input bank where the clock oscillators are connected to. that
bank is a Vcco=3.3V bank but has a 2.5V LVDS connection, but since
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&ge
tPagePath=16830
 says this is not a problem i hope this is not the problem.

Now the problem is that when i download the code and boot chipscope
analyzer, the analyzer says it does not find any core (although there is a
ICON/ILA core in it) and when i check with fpga editor there is indeed a
ICON/ILA core. So that is why i thought that the clock generation is a
problem (although the clk's are generated since i can see them at the input
pad of the fpga)? especially since i cannot get anything out of the fpga,
everything remains inactive for some reason...

i also get this warning:

ARNING:Xst:1474 - Core <vio> was not loaded for <i_vio> as one or more ports
did not line up with component declaration.  Declared input port
<control<35>> was not found in the core.  Please make sure that component
declaration ports are consistent with the core ports including direction and
bus-naming conventions.
WARNING:Xst:1474 - Core <ila2> was not loaded for <i_ila2> as one or more
ports did not line up with component declaration.  Declared input port
<control<35>> was not found in the core.  Please make sure that component
declaration ports are consistent with the core ports including direction and
bus-naming conventions.
WARNING:Xst:1474 - Core <ila1> was not loaded for <i_ila1> as one or more
ports did not line up with component declaration.  Declared input port
<control<35>> was not found in the core.  Please make sure that component
declaration ports are consistent with the core ports including direction and
bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or more
ports did not line up with component declaration.  Declared output port
<control0<3>> was not found in the core.  Please make sure that component
declaration ports are consistent with the core ports including direction and
bus-naming conventions.

but since i've seen this warning in the past and chipscope worked i don't
think this is the problem.

I hope some of you know where i can start looking since for now i don't have
a clue ...

kind regards,

Yttrium