Hi Austin,

[snip]

> Seems like a simple problem to me:  choose H2 and have a potentially
> career limiting experience, or choose EasyPath and go home happy every
> night....

FPGA's are often touted as high-cost (sorry, A, A, L and X are)
risk-mitigating devices versus ASIC. EasyPath users would indeed be the
types who find the risk/delay involved with saving money by going to any
kind of ASIC completely unacceptable but are running enough volume to
recover the NRE charge for Easypath.

HC2 is supposed to sit between standard cell and FPGA (much closer to
standard cell, I'll give you), which should find some high-volume customers
with fast time-to-market and pricing requirements that are too tight for
EasyPath but are not comfortable with standard-cell risk and development
time.  If you're making a flat-panel TV, a single cent saved in item cost
is easily recovered in NRE, signal integrity testing etc. Unfortunately
these cents are also saved by using crappy connectors, bad crystals, flaky
switches etc, but that's not the issue here. People in Purchasing do take
these risks...

The markets for both solutions are different.

One sort-of compelling thing about HC2 on the engineering side, by the way
is this: have you ever designed an ASIC from a nice and user-friendly GUI?
With Quartus you can...

Oh, and I know someone who was fired for choosing IBM...

Best regards,


Ben

Ben,

-snip-

> Sounds quite reasonable. So, technologically there's nothing holding Altera
> back in investing in a few extra ("standard") device testers and, as an
> intermediate price-reduction step, doing same under the hereby trademarked
> name "Crippledie" (come to think of it, sounds great as the title of an
> ultra-violent FPS game taking place in a hospital or a leper colony too -
> I'll have a chat with my local EA Games marketing guy).

Except that 'EasyPath' has patents pending with a number of claims that 
would prevent Altera from having an EasyPath clone (without paying us 
for the rights to do so).

> I can't imagine that only partially testing an ASIC is patentable - but then
> again, one-click-shopping is patentable as well according the USPTO so I
> wouldn't be surprised.

Imagine if you will a car company that makes a top of the line car, and 
sells it for a lot of money.  Now emagine the same company establishing 
a different distributorship for a lower cost version of the similar car, 
less chrome, less power windows, etc. (but basically all the same 
subcomponents).

Happens all the time, doesn't it?

Jaguar/Volvo/Lincoln/Ford.  Buick/Potiac/GMC/Chevy.  Lexus/Toyota. ...

> 
> Then of course there's HardCopy2, which, like EasyPath, only needs to be
> tested with the user design _but also_ is a lot smaller in die size. 
> 
> Thus:
> 
> Better Yield+Shorter Time+Smaller Area = Even Lower Cost to Altera, which
> means even Lower Prices to customer. No ECO and no last-minute changes
> though, I'll give you that.
> 
> Am I right?

Yes, but ....

An ASIC is always going to be lower cost, only if the volume can 
overcome the NRE cost.  Now if Altera is happy to eat a majority of the 
NRE, and have lower margins (which, by the way they announced last 
financial report), then the customer benefits (obviously).

But, for every change, the whole cost picture is thrown out, as the line 
stops until the new good parts can be delivered.

Since H2 is not even pin compatible with the S2, the pcb must be 
redesigned.  In some cases (most) the signal integrity analysis of all 
IOs must be repeated.  I have heard a case where the cost of the H2 is 
very high, as the package is very expensive (that the customer wants).

To go from flip chip, back to a cheap wirebond package may result in 
Signal Integrity issues that can not be solved!

(By the way, I will not even go into how the H2 is not even a logic 
equivalent to S2:  there are features and components that are just 
different between the two!)

With EasyPath, you go from the working solution, to a less costly 
working solution with no redesign whatsover, and no risk at all.

Seems like a simple problem to me:  choose H2 and have a potentially 
career limiting experience, or choose EasyPath and go home happy every 
night....

Austin

Hi Ben Jones,

> Shorter time? Lower cost? For an ASIC conversion product versus an FPGA?
> Surely you jest, sir! So the mask set just magically creates itself and
> pays for itself now, or what?

OK, ok, forgot about the NRE to create the wiring/config layers. Blushing
here. Then again, as far as I know, the setting up of the EasyPath part's
testing program isn't free either.

However, once actual HC2 production of a design has started, most definitely
yes - most layers are pre-fabricated, so once a certain design batch needs
to be produced, only the top few (2? 3?) metal layers need to be deposited,
either from from stock wafers or straight in the production pipe.

Also, assuming the same number of wafer defects (it's the same process after
all), given the smaller die, the yield will automatically be higher.

Best regards,


Ben

> Then of course there's HardCopy2, which, like EasyPath, only needs to be
> tested with the user design _but also_ is a lot smaller in die size.
> Thus:
> Better Yield+Shorter Time+Smaller Area = Even Lower Cost to Altera, which
> means even Lower Prices to customer. No ECO and no last-minute changes
> though, I'll give you that.

Shorter time? Lower cost? For an ASIC conversion product versus an FPGA?
Surely you jest, sir! So the mask set just magically creates itself and pays
for itself now, or what?

        -Ben-

Hi Austin,

>> So, can I then summarize that EasyPath is basically a standard Virtex
>> II/4 but with less time on the testbed (only the cells and routing used
>> by the customer are tested) in order to reduce cost?
> 
> There is a basic 1's, 0's, shorts, leakage, etc test done to all parts,
> EasyPath or no.

Of course. The global die specs must be met.

> And then, for EasyPath, only those features used by the customer are
> tested (with the addition of any LUT pattern for the CLBs they use, and
> any IO strength for th IOB standard they use, which allows for the two
> most common ECO requests we got after we shipped).  The difference in
> test time between as close as we can get to 100% testing for any
> possible use, and as close as we can get to 100% testing for one use is
> SIGNIFICANT.

Sounds quite reasonable. So, technologically there's nothing holding Altera
back in investing in a few extra ("standard") device testers and, as an
intermediate price-reduction step, doing same under the hereby trademarked
name "Crippledie" (come to think of it, sounds great as the title of an
ultra-violent FPS game taking place in a hospital or a leper colony too -
I'll have a chat with my local EA Games marketing guy).

I can't imagine that only partially testing an ASIC is patentable - but then
again, one-click-shopping is patentable as well according the USPTO so I
wouldn't be surprised.

Then of course there's HardCopy2, which, like EasyPath, only needs to be
tested with the user design _but also_ is a lot smaller in die size. 

Thus:

Better Yield+Shorter Time+Smaller Area = Even Lower Cost to Altera, which
means even Lower Prices to customer. No ECO and no last-minute changes
though, I'll give you that.

Am I right?

Best regards,



Ben

Adam Megacz wrote:

>Austin Lesea <austin@xilinx.com> writes:
>  
>
>>Better Yield + Shorter Time = Lower Cost to Xilinx, which means Lower
>>Prices to customer.
>>    
>>
The point is, the easy path parts are not known defects, they are simply 
not tested as rigorously as the non-easy-path parts.  Basically, they 
reduce the test program to test only what your bitstream actually uses 
in the design (and some testing of other unused logic, but not nearly as 
rigorous).  The result is significantly reduced testing time and 
increased yield, which translates into a cost savings.  What they 
guarantee that way is only that it will work with your bitstream.  It 
could be a perfectly good part, or it could have a defect somewhere 
where it doesn't affect your design.  No one knows, because no one 
tested it.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Austin Lesea <austin@xilinx.com> writes:
> Better Yield + Shorter Time = Lower Cost to Xilinx, which means Lower
> Prices to customer.

I'm assuming it's mostly "better yield", though, right?  I mean,
Atmel's chips can 100% test themselves (they'll even give you the
bitstream that does it), and I'd bet that the XC6200 could've (or
probably even did).

Isn't the test time just a matter of "assembly line latency" rather
than "assembly line throughput"?  It shouldn't be like an ASIC where
you need a separate, active device to test it and those devices are in
short supply.

Forgive me if this sounds stupid.  My knowledge gets pretty fuzzy down
at the fabrication/process level.

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

Ben -

Although I haven't used Xilinx' EasyPath product, it makes a fair
amount
of sense.  I've used V2Pro parts for a while, but I don't care about
or use the PowerPC processor I get in the the part.  EasyPath would
let me get cheaper parts in volume for 2 reasons -

a) Xilinx doesn't even have to test the PPC core in parts they would
ship
to me.  They save dollars because of chip test time saving.

b) Xilinx could send me parts with dead PPC cores since I don't use
that feature.  I assume the PPC core takes a reasonable amount of
silicon area, so it would have a reasonable chance of having a
defect.  Those 'dead' chips are currently lost revenue to Xilinx, the
incremental cost to sell them to me is fairly low.

I don't know how the EasyPath cost compares to the Altera HardCopy2,
but it sure makes sense that EasyPath could offer nice savings for
the volume user and additional profit for Xilinx.  A win-win situation.

John Providenza

Ben,

-snip-
> 
> 
> So, can I then summarize that EasyPath is basically a standard Virtex II/4
> but with less time on the testbed (only the cells and routing used by the
> customer are tested) in order to reduce cost?

There is a basic 1's, 0's, shorts, leakage, etc test done to all parts, 
EasyPath or no.

And then, for EasyPath, only those features used by the customer are 
tested (with the addition of any LUT pattern for the CLBs they use, and 
any IO strength for th IOB standard they use, which allows for the two 
most common ECO requests we got after we shipped).  The difference in 
test time between as close as we can get to 100% testing for any 
possible use, and as close as we can get to 100% testing for one use is 
SIGNIFICANT.

As well, the test yield to one test program is also SIGNIFICANTLY HIGHER 
than for many thousands of test programs (which is potentially what it 
takes to have an acceptable AQL).

Better Yield + Shorter Time = Lower Cost to Xilinx, which means Lower 
Prices to customer.

Austin