My apologies for not responding to this: my computer crashed big-time, & 
is only now on the air again.
I see several others took up the thread: I trust you got satisfactory 
advice from them.

Emtech wrote:
> Hi David
> Th
> is is for an RGB LED demo display application.
> 
> 1. There will be mixing of colours done at say 3ms intervals for each colour
>     to stay ithin the 10ms and take avantage of persistance of vision.
> 2. Bits accuracy in the duty cycle is not very important since the PWM is
>     only for brightness control.
> 3. The outputs must at least be synchronized to the colour mixing intervals,
>     i.e. 3ms intervals.  In other words, the PWM will further divide the 3ms
>     intervals to control brightness.
> 4. These will only be used in an RGB LED display application hence the only
>     real importance is the 10ms refresh limit.
> 
> Thank you for your input.
> Peter.
> 
> "David Brooks" <davebXXX@iinet.net.au> wrote in message 
> news:435d7280$0$8621$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> 
>>Can you further tell us:
>>1. What pulse repetition frequency you want
>>2. How many bits accuracy in the duty cycle
>>3. Must the outputs be synchronised?
>>4. Are they to drive model-control servos? (Those often respond not to the 
>>average energy in the signal, but to the actual width. You can have a very 
>>long interval between pulses, & still have them work).
>>
>>Emtech wrote:
>>
>>>I have an application where I need to implement 24 or up to 32 PWM 
>>>outputs (8-bit) and
>>>am considering using a small CPLD to handle the PWMs instead of doing it 
>>>all in software.
>>>This does add a CPLD to the design, but frees the micro do to other 
>>>things.
>>>
>>>Any recommendations on the CPLD & CPLD size without completing the VHDL 
>>>first?
>>>
> 
> 

Emtech wrote:
> This is for an RGB LED demo display application.
> 
> 1. There will be mixing of colours done at say 3ms intervals for
 >    each colour to stay ithin the 10ms and take avantage of
 >    persistance of vision.
> 2. Bits accuracy in the duty cycle is not very important since
 >    the PWM is only for brightness control.
> 3. The outputs must at least be synchronized to the colour mixing
 >    intervals, i.e. 3ms intervals.  In other words, the PWM will
 >    further divide the 3ms intervals to control brightness.
> 4. These will only be used in an RGB LED display application
 >    hence the only real importance is the 10ms refresh limit.
> 
> Thank you for your input.

Very interesting. Earlier this year I did a PWM design to control
RGB LEDs for a medical testing device. The client wanted a total
of 61 RGB LEDs, or 183 channels of PWM output, with 16-bit
resolution and 1 ms refresh period (Yes, this means a 65.536 MHz
clock). I divided this up into three Xilinx Spartan-3 FPGAs with
63 PWM output channels each in order to avoid BGA packages and
simplify the overall PCB layout. Each FPGA drives 20 or 21 RGB
LED chips.

IIRC, it didn't quite fit into an XC3S50, so we ended up using
the XC3S200. A design with less resolution or fewer channels
would easily fit into the smaller chip.

The PWM hardware is driven entirely by the contents of a single
block RAM, and uses one of the RAM's ports to read out the data.
This gives a great deal of flexibility as to how the system
controller gets the intensity values into the RAM via its other
port, using anything from a conventional parallel bus interface
to a synchronous or asynchronous serial interface.

-- Dave Tweed

"Emtech" <noaddress> skrev i meddelandet news:435cb632@news.eftel.com...
>I have an application where I need to implement 24 or up to 32 PWM outputs 
>(8-bit) and
> am considering using a small CPLD to handle the PWMs instead of doing it 
> all in software.
> This does add a CPLD to the design, but frees the micro do to other 
> things.
>
> Any recommendations on the CPLD & CPLD size without completing the VHDL 
> first?
>

If  you want to use a minimal amount of CPU power, then
you could connect a CPLD to a time slot bus and transfer frames of 32 x 8 
bit = 256 bits
containing the PWM data.

The CPLD would contain

An 8 bit counter for determining bitnumber in each frame.
    The upper 5 bits select PWM output
An 8 bit PWM counter.
    Each PWM value is compared to the PWM counter and the PWM output bit is 
set if the value is less than the PWM counter.
32 PWM outputs
    A 64 macrocell CPLD should do the job.

You can get an I2S function in an AT91SAM7S321 ARM micro
-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB 

Emtech wrote:
> Hi David
> Th
> is is for an RGB LED demo display application.
> 
> 1. There will be mixing of colours done at say 3ms intervals for each colour
>     to stay ithin the 10ms and take avantage of persistance of vision.
> 2. Bits accuracy in the duty cycle is not very important since the PWM is
>     only for brightness control.
> 3. The outputs must at least be synchronized to the colour mixing intervals,
>     i.e. 3ms intervals.  In other words, the PWM will further divide the 3ms
>     intervals to control brightness.
> 4. These will only be used in an RGB LED display application hence the only
>     real importance is the 10ms refresh limit.
> 
> Thank you for your input.
> Peter.

  That speed is low enough to allow any nimble 8 bit-uC to do the task.

eg SiLabs have many to choose from, forthe 80C51 each PWM operation is 2 
lines of assembler (or 2+1/8 lines of assembler, if you want better time 
alignment).
  Then you can add things like gamma correction, and colour skew 
correction, and even LED calibration in Flash....

-jg

There are many ways to implement this, at your extremely low rate even
more than many.
But if the present state needs to be stored, you need 256 storage
elements on-chip, and that makes a CPLD rather expensive.
The smallest FPGA does this job hands down.
Your job is expensive in a CPLD, trivial in any FPGA.
If you only want to make one demonstrator, buy an FPGA eval board, and
finish the job in no time.

Peter Alfke

Hi David
Th
is is for an RGB LED demo display application.

1. There will be mixing of colours done at say 3ms intervals for each colour
    to stay ithin the 10ms and take avantage of persistance of vision.
2. Bits accuracy in the duty cycle is not very important since the PWM is
    only for brightness control.
3. The outputs must at least be synchronized to the colour mixing intervals,
    i.e. 3ms intervals.  In other words, the PWM will further divide the 3ms
    intervals to control brightness.
4. These will only be used in an RGB LED display application hence the only
    real importance is the 10ms refresh limit.

Thank you for your input.
Peter.

"David Brooks" <davebXXX@iinet.net.au> wrote in message 
news:435d7280$0$8621$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Can you further tell us:
> 1. What pulse repetition frequency you want
> 2. How many bits accuracy in the duty cycle
> 3. Must the outputs be synchronised?
> 4. Are they to drive model-control servos? (Those often respond not to the 
> average energy in the signal, but to the actual width. You can have a very 
> long interval between pulses, & still have them work).
>
> Emtech wrote:
>> I have an application where I need to implement 24 or up to 32 PWM 
>> outputs (8-bit) and
>> am considering using a small CPLD to handle the PWMs instead of doing it 
>> all in software.
>> This does add a CPLD to the design, but frees the micro do to other 
>> things.
>>
>> Any recommendations on the CPLD & CPLD size without completing the VHDL 
>> first?
>> 

Can you further tell us:
1. What pulse repetition frequency you want
2. How many bits accuracy in the duty cycle
3. Must the outputs be synchronised?
4. Are they to drive model-control servos? (Those often respond not to 
the average energy in the signal, but to the actual width. You can have 
a very long interval between pulses, & still have them work).

Emtech wrote:
> I have an application where I need to implement 24 or up to 32 PWM outputs 
> (8-bit) and
> am considering using a small CPLD to handle the PWMs instead of doing it all 
> in software.
> This does add a CPLD to the design, but frees the micro do to other things.
> 
> Any recommendations on the CPLD & CPLD size without completing the VHDL 
> first?
> 
> 

On Mon, 24 Oct 2005 20:24:10 +1000, "Emtech" <noaddress> wrote:

>I have an application where I need to implement 24 or up to 32 PWM outputs 
>(8-bit) and
>am considering using a small CPLD to handle the PWMs instead of doing it all 
>in software.
>This does add a CPLD to the design, but frees the micro do to other things.
>
>Any recommendations on the CPLD & CPLD size without completing the VHDL 
>first?
>
one or more  slave microcontrollers, doing the PWM in software will probably be a lot cheaper than a
PLD/FPGA solution if the speed you need isn't excessively high. Something like PIC16F914 or one of
the lower end ATMEGA range should do the job. 
Obviously there will be tradeoffs between PWM rate, resolution, pin-count and cost that will
determine the optimum number of micros, but even if you needed 4 MCUs doing 8 channels each it would
be a lot cheaper than a CPLD or FPGA solution,

Another solution worth thinking about is a hybrid mcu/CPLD solution - if it would be possible to
stagger the PWM phase, then the MCU could output the PWM value for each channel at the start of each
cycle, then the external logic resources would be reduced to a set of loadable 8-bit down-counters,
which would be more amenable to fitting in a cheap CPLD

 


 

"Emtech" <noaddress> schrieb im Newsbeitrag news:435cb632@news.eftel.com...
> I have an application where I need to implement 24 or up to 32 PWM outputs
> (8-bit) and
> am considering using a small CPLD to handle the PWMs instead of doing it
all
> in software.
> This does add a CPLD to the design, but frees the micro do to other
things.
>
> Any recommendations on the CPLD & CPLD size without completing the VHDL
> first?
>
>

if you think small PLD is cheap then thing again.
for 32 x 8 bit PWM you need 256 flips flops only to hold the PWM values.
those you would need 384 MC PLD or larger. now look at the prices.

using an low cost FPGA would be cheaper, or possible MAX2 or machXO device.
if you have cheap flash memory to hold FPGA config use LatticeEC or small
spartan
if not then look at MAX2 or MachXO - those are advertized as PLD but are in
fact
small simple FPGA with nonvolatile config. or LatticeXP what is nonvolatile
FPGA

antti

I have an application where I need to implement 24 or up to 32 PWM outputs 
(8-bit) and
am considering using a small CPLD to handle the PWMs instead of doing it all 
in software.
This does add a CPLD to the design, but frees the micro do to other things.

Any recommendations on the CPLD & CPLD size without completing the VHDL 
first?