Stephane,

http://www.xilinx.com/cgi-bin/power_tool/power_Virtex4

is a new version of the web power tool, but for the full ISE 8.1i, I 
think that is still yet to be announced ... soon.

Austin

Stephane wrote:

> Hi Austin,
> 
> when are we to expect 8.1i ?
> 
> BR
> 
> Austin Lesea wrote:
> 
>> http://direct.xilinx.com/bvdocs/userguides/ug071.pdf
>>
>> page 69 (1312 bits, of which 12 are the FRAME_ECC syndrome), and 
>> continuing
>>
>> and
>>
>> http://direct.xilinx.com/bvdocs/appnotes/xapp714.pdf
>>
>> So a larger device has a number of vertical frames (not just two).
>>
>> Austin
>>
>> Andreas Nett wrote:
>>
>>> Hello everybody,
>>>
>>> I'm working on dynamic partial reconfiguration of Xilinx Virtex-II 
>>> FPGAs. In all Virtex-Device-Families the smallest (re-)configurable 
>>> unit is a FRAME. I know that in Virtex and Virtex-II, these Frames 
>>> are running from the top of the device to the bottom. This means that 
>>> during reconfiguration of a module in the center of the device, no 
>>> signals can get from the left side to the right side.
>>>
>>> I heard that in Virtex-4, frames didn't go from the top of the device 
>>> to the bottom but, that there were upper and a lower frames which 
>>> could also be addressed separately. This would be helpful, concerning 
>>> the problem described above. Unfortunately I didn't find any 
>>> information on this topic in the Xilinx Data Sheets.
>>>
>>> Now, my question is: Are there upper and lower frames in a Virtex-4? 
>>> Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?
>>>
>>> Thanks in advance Andreas

Hi Austin,

when are we to expect 8.1i ?

BR

Austin Lesea wrote:

> http://direct.xilinx.com/bvdocs/userguides/ug071.pdf
> 
> page 69 (1312 bits, of which 12 are the FRAME_ECC syndrome), and continuing
> 
> and
> 
> http://direct.xilinx.com/bvdocs/appnotes/xapp714.pdf
> 
> So a larger device has a number of vertical frames (not just two).
> 
> Austin
> 
> Andreas Nett wrote:
> 
>> Hello everybody,
>>
>> I'm working on dynamic partial reconfiguration of Xilinx Virtex-II 
>> FPGAs. In all Virtex-Device-Families the smallest (re-)configurable 
>> unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are 
>> running from the top of the device to the bottom. This means that 
>> during reconfiguration of a module in the center of the device, no 
>> signals can get from the left side to the right side.
>>
>> I heard that in Virtex-4, frames didn't go from the top of the device 
>> to the bottom but, that there were upper and a lower frames which 
>> could also be addressed separately. This would be helpful, concerning 
>> the problem described above. Unfortunately I didn't find any 
>> information on this topic in the Xilinx Data Sheets.
>>
>> Now, my question is: Are there upper and lower frames in a Virtex-4? 
>> Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?
>>
>> Thanks in advance Andreas

http://direct.xilinx.com/bvdocs/userguides/ug071.pdf

page 69 (1312 bits, of which 12 are the FRAME_ECC syndrome), and continuing

and

http://direct.xilinx.com/bvdocs/appnotes/xapp714.pdf

So a larger device has a number of vertical frames (not just two).

Austin

Andreas Nett wrote:

> Hello everybody,
> 
> I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.
> 
> I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.
> 
> Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?
> 
> Thanks in advance Andreas

Andreas Nett wrote:
> Hello everybody,
> 
> I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.
> 
> I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.
> 
> Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?
> 
> Thanks in advance Andreas


The height that a frame covers is a clock region, and the number of 
regions depends of your V4 size.

You'll find additional infos on the dedicated mailing list:
http://www.itee.uq.edu.au/~listarch/partial-reconfig/

Don't loose time with the tools: it is said that ISE 8.1i will address 
this issue with V4, but yet I've seen no date of availability. Anyone?

Hello everybody,

I'm working on dynamic partial reconfiguration of Xilinx Virtex-II FPGAs. In all Virtex-Device-Families the smallest (re-)configurable unit is a FRAME. I know that in Virtex and Virtex-II, these Frames are running from the top of the device to the bottom. This means that during reconfiguration of a module in the center of the device, no signals can get from the left side to the right side.

I heard that in Virtex-4, frames didn't go from the top of the device to the bottom but, that there were upper and a lower frames which could also be addressed separately. This would be helpful, concerning the problem described above. Unfortunately I didn't find any information on this topic in the Xilinx Data Sheets.

Now, my question is: Are there upper and lower frames in a Virtex-4? Or do Virtex-4 frames look like the frames in Virtex and Virtex-II?

Thanks in advance Andreas