> Hi All,
>
> I have a embedded desig where I communicate with two boards via Fast
> ethernet. The design is very simple, the packets are generated from a
> fpga and sent to the ethernet phy on MII. In the new design I'd like to
> replace the ethernet phy with a VSDL2 chipset, so I need only one
> twisted pair and for supporting more than 100 m.
> Has anybody did something similar? IMO it should be very straight
> forwarded to replace the phy with a VDSL2 chipset, but please let me
> know if I'm wrong.
>
> Regards,
>
> Kim
>
It is not clear what you are really trying to achieve, and whether VDSL2
is the right solution. There may be better options for connecting two
boards in a more standard way, though I don't know what would meet your
needs best.
Do you need to maintain the high data rate over a much greater distance,
and is it really important to achieve the high rate over only one pair?
If you can live with the 100m restriction or less, and use standard
cabling, it sounds simpler to stick with what you have.
I have done something similar but it was before VDSL2, and I had access
to proprietary hardware.
You will probably be restricted by whatever interface the chipset
provides, even if you can get hold of the chipsets. And it is likely to
be a lot of effort to design something which will always be non-standard.
Reply by Simon Peacock●December 8, 20052005-12-08
Unfortunately finding a VDSL2 chip might be difficult.
As with most PSTN specs, the customer end is easy, the telcom end is a bit
more problematic. Telco's don't want individual ports, they want 2,000 ...
so that's what they get.
It also looks a bit bleeding edge.. so try to stick with one supplier to
avoid interoperability issues.
Simon
<fpgakid@gmail.com> wrote in message
news:1134066178.467301.202070@g14g2000cwa.googlegroups.com...
> Hi All,
>
> I have a embedded desig where I communicate with two boards via Fast
> ethernet. The design is very simple, the packets are generated from a
> fpga and sent to the ethernet phy on MII. In the new design I'd like to
> replace the ethernet phy with a VSDL2 chipset, so I need only one
> twisted pair and for supporting more than 100 m.
> Has anybody did something similar? IMO it should be very straight
> forwarded to replace the phy with a VDSL2 chipset, but please let me
> know if I'm wrong.
>
> Regards,
>
> Kim
>
Reply by fpga...@gmail.com●December 8, 20052005-12-08
Hi All,
I have a embedded desig where I communicate with two boards via Fast
ethernet. The design is very simple, the packets are generated from a
fpga and sent to the ethernet phy on MII. In the new design I'd like to
replace the ethernet phy with a VSDL2 chipset, so I need only one
twisted pair and for supporting more than 100 m.
Has anybody did something similar? IMO it should be very straight
forwarded to replace the phy with a VDSL2 chipset, but please let me
know if I'm wrong.
Regards,
Kim