Sorry, Erez and FPGA friends,

Thank you for your advices. After making sure that OBUFs were instantiated
properly, I further found out that I didn't check all my external pin
connectors on the FF1152 board, which were welded by some company. I was so
lucky (?) that I happened to use the specific external pin that was not
well-connected to the GCLK pad on the board. Hence my clock was fed to that
pad in vain. Everything went fine after I assigned the clock to another GCLK
pad.

Sorry for this result, but also thank you for your help :-)

Regards,
Merlin

"Erez Birenzwig" <erez_birenzwig@hotmail.com> wrote in message news:<NYasb.998$%o4.33145@news.xtra.co.nz>...
> I found out that the DDR FF is optimized out if you do not connect
> it to a OBUF of some kind.
> If you use a synthesis tool you might want to declare the pin as output
> of some kind (Select IO), or just instantiate the OBUF directly in the HDL.
> 
> Erez.
> 
>

I found out that the DDR FF is optimized out if you do not connect
it to a OBUF of some kind.
If you use a synthesis tool you might want to declare the pin as output
of some kind (Select IO), or just instantiate the OBUF directly in the HDL.

Erez.


"Jiang" <merlin_jiang@hotmail.com> wrote in message
news:9bd94bca.0311110028.294412a9@posting.google.com...
> Hello, FPGA friends,
>
> I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with
an
> FF1152 board. My ISE is version 5.2.03i. In the beginning I could do a
trivial
> bypassing using Virtex 2000E with a BG560 board:
>
> input clk;
> output out_clk;
> wire out_clk;
>
> out_clk=clk;
>
> But on my Virtex-II 6000 it didn't work. It's fine since that I could try
> FDDRRSE to accomplish the same task. My code evolved as:
>
> input clk;
> output out_clk;
> wire out_clk;
>
> FDDRRSE fddrrse_0 (
> .Q (out_clk),
> .C0 (clk),
> .C1 (~clk),
> .CE (1'b1),
> .D0 (1'b1),
> .D1 (1'b0),
> .R (1'b0),
> .S (1'b0)
> );
>
> After browsing the old messages of this news group, I didn't know why the
above
> code failed again. The output port just stuck at logic 0, and it looked
like
> that fddrrse_0 was power-up and did nothing. Then I tried to use Xilinx
> floorplanner to see what FDDRRSE was. Here I found it not
> being floorplanned. Well, maybe it was too trivial to be floorplanned.
Hence
> I used Xilinx FPGA editor to see what the connections were like. However,
> besides my fddrrse_0, I didn't find any nets other than the I/O port
between
> the inferred input and output buffers and some VCCs. And it looked like
> clk --> clk_IBUFG --> out_clk was the whole route.
>
> I believe I might have missed something there such that neither could I
> bypass clock signals correctly nor could I understand what Xilinx
floorplanner
> and FPGA editor told me.
>
> Please give me some suggestion to understand even some parts of this
problem.
> Thank you :-)
>
> Regards,
> Merlin

Hello, FPGA friends,

I'm trying to implement a simple clock bypassing on my Virtex-II 6000 with an
FF1152 board. My ISE is version 5.2.03i. In the beginning I could do a trivial
bypassing using Virtex 2000E with a BG560 board:

input clk;
output out_clk;
wire out_clk;

out_clk=clk;

But on my Virtex-II 6000 it didn't work. It's fine since that I could try
FDDRRSE to accomplish the same task. My code evolved as:

input clk;
output out_clk;
wire out_clk;

FDDRRSE fddrrse_0 (
.Q (out_clk), 
.C0 (clk), 
.C1 (~clk), 
.CE (1'b1), 
.D0 (1'b1), 
.D1 (1'b0), 
.R (1'b0), 
.S (1'b0)
);

After browsing the old messages of this news group, I didn't know why the above
code failed again. The output port just stuck at logic 0, and it looked like
that fddrrse_0 was power-up and did nothing. Then I tried to use Xilinx
floorplanner to see what FDDRRSE was. Here I found it not
being floorplanned. Well, maybe it was too trivial to be floorplanned. Hence
I used Xilinx FPGA editor to see what the connections were like. However,
besides my fddrrse_0, I didn't find any nets other than the I/O port between
the inferred input and output buffers and some VCCs. And it looked like
clk --> clk_IBUFG --> out_clk was the whole route.

I believe I might have missed something there such that neither could I
bypass clock signals correctly nor could I understand what Xilinx floorplanner
and FPGA editor told me.

Please give me some suggestion to understand even some parts of this problem.
Thank you :-)

Regards,
Merlin