Reply by June 8, 20212021-06-08
```Well, I personally don't know any algorithm to convert a "large number in binary format into any base n, with n being a prime number" that would be a good fit for FPGAs.
Na&iuml;ve algorithms make use of division operations, and FPGA are not good at these operations.
But that skip method seems to be very promising... but it may need a lot of investigation/exploration/analysis/research from my point of view....But I really can see that the gain in skipping values is really major, I simply cannot think right now in a good "architecture" to implemented it!

What I can show you is where FPGAs shine. I wrote a module in Verilog code that can be synthesizable at 100 MHz (barely!) for a Zynq 7020 when retiming is used (basically I did not pipelined the design, but used some of the tools options that tries to do it for me) and that makes use of around 2100 LUTS.

The concept idea for the system would be the following:

There would be an application running in an PC (written in C, C#, Python, whatever language it would be preferred) that would create jobs to be distributed to boards with FPGA devices (either through Ethernet, or simply through UART). In a FPGA device it would exist at least one (Soft) processor connected to many of these modules,  to which those jobs are distributed. These jobs would consist in 2 72-bit numbers, one at which the processing would start, another at which the processing would end. (The module requires that the Start Number would be converted to each n Base by the (Soft) Processor before it starts processing).

The description of the module is the following:

For each base (2, 3, 5, 7, 11, 13, 17)  there is a counter of that base, which at every and each 1 clock cycle advances one unit. In pipeline and in parallel with these counters there is a tree of adders ( well for base 2 the popcount module is used) to sum up all the "digits" values of that number for each base. To avoid adders with more than 7 bits, overflow flag is used whenever a sum does not fit in 7 bits. At one point every adder of each base n is compared with each other. If none overflowed, and if all have the same value then this is a relevant value, and outputs this signal.

The module that I designed is not finished, is a proof of concept, it may have bugs, but has been designed to show how to generate sequences A135127, A212222, A335839 and the next sequence of &ldquo;Integers whose sum of digits in base b is the same for every prime b up to 17.&rdquo;

It can be found in:  https://www.edaplayground.com/x/AUaM

For the people that will look into the code, sorry for the lack of comments&hellip; just wanted to try out some things. For instance, a counter with 72 bits running at 100MHz is not something that I have done in the past (for low end FPGAs), or tree adders with like 20 7-bit adders running at the same 100MHz&hellip; These would ideally be pipelined by hand, but I got away with the tools options, after inserting a few pipeline registers. The 100 MHz objective would be easier to achieve if less bits would be used&hellip;

One module like this would process 100M numbers per second,  and for the A335839  sequence would process up to 4294899857375(base 10) in half a day (Am I doing the math correctly? 4294899857375 / 100000000 /3600/ 24 = 0.49709!)

Don&rsquo;t know why your target is 72-bits and above,  but with less bits (lets say 64-bits numbers) 100MHz would be better achievable, and in a 150&euro; FPGA board, it would fit 12/15 of these modules.

Regards,
Nelson
```
Reply by June 4, 20212021-06-04
```Richard Damon <Richard@Damon-Family.org> schrieb:
> On 5/10/21 3:09 AM, Thomas Koenig wrote:
>> Richard Damon <Richard@Damon-Family.org> schrieb:
>>> I suppose the big question is how big of gaps do you tend to find, If it
>>> can jumps thousands of values, it could well be worth it, and I suppose
>>> it well could be. I could see the binary represtation could establish an
>>> upper bound for the sum of digits, and if higher order digits of some
>>> base exceed that value, you know you need to increment till those
>>> change, which could be a very big jump.
>>
>> You are right, the gaps are indeed huge, and the gains enormous.
>>
>> If I limit myself to 72 bits, I have around 4.72237E+21 possible
>> binary numbers, but "only" 2.91386E+18 eligible numbers base 17 which
>> have a sum of digits of 72 or less, so this is a reduction by
>> a factor of 1600 alone, more if you look at the actual ranges
>> rather than the maximum as I did above.  For base 13, the factor
>> is around 120, for 11 it is 50.
>>
>
> It sounds like this skip will be key to processing, and I suspect that
> only using the highest base will probably get you enough to be
> practical, and will allow still good speed.

Maybe a bit of an update here.

I have since implemented two algorithms which gave me an
enormous speedup on traditional CPUs.

Key to both algorithms is a function which returns the range of
the sums of digits base n between integers a and b.  For base 2,
this is particularly efficient.

One method is a recursive binary search - given a range between a
and b, it checks if, for all bases looked at, the ranges of sums
of digits intersect.  If they don't, return.  If they do, partition
into two parts and look again for each one.

The second is the skip function you mentioned above.  If it
is given a base-17 number like, it looks for the next largest
number with one more zero digit at the end, like this:

01 03 16 04 03
01 03 16 05 00
01 04 00 00 00
01 04 00 00 00
02 00 00 00 00

(have to watch for carries there) and tests at each stage if the
sum of digits base 2 in the range between the original number
and the new one is still valid.

This is _extremely_ efficient - at a high number range, this can
give skips of 17^10 or so.  I alternate this base 17, base 13 and
base 11.

This has allowed me to find numbers which have the same
number of digits in base 17, 13, 11, 5 and 5 (not 3), like
7172806004621143883825103 (which is larger than 2^82).  There are
very few of those, and none have so far had the same sum of digits
in base 3.

A key to speed is obviously the time in which a large number
in binary format can be converted into base n.  Is an FPGA
the right tool for that?
```
Reply by May 10, 20212021-05-10
```On 5/10/21 3:09 AM, Thomas Koenig wrote:
> Richard Damon <Richard@Damon-Family.org> schrieb:
>> I suppose the big question is how big of gaps do you tend to find, If it
>> can jumps thousands of values, it could well be worth it, and I suppose
>> it well could be. I could see the binary represtation could establish an
>> upper bound for the sum of digits, and if higher order digits of some
>> base exceed that value, you know you need to increment till those
>> change, which could be a very big jump.
>
> You are right, the gaps are indeed huge, and the gains enormous.
>
> If I limit myself to 72 bits, I have around 4.72237E+21 possible
> binary numbers, but "only" 2.91386E+18 eligible numbers base 17 which
> have a sum of digits of 72 or less, so this is a reduction by
> a factor of 1600 alone, more if you look at the actual ranges
> rather than the maximum as I did above.  For base 13, the factor
> is around 120, for 11 it is 50.
>

It sounds like this skip will be key to processing, and I suspect that
only using the highest base will probably get you enough to be
practical, and will allow still good speed.

Build the system with 1 (small FPGA), 17 (medium FPGA), or 17^2 (large
FPGA) of these computation cores.

The incrementer rather than being a fixed increment gets the increment
to do from logic looking at the sum of the upper digits of the base 17
number of the first unit, and will add a power of 17 to the current
numbers in all the bases. You will just precompute the powers of 17 in
the bases you are using.

If you start at 0, then the first unit will only roll its upper digits
when all the digits below that digit are zero, so we can rapidly skip by
just adding repeatedly that power of 17 to the sum.

Yes, we could compute a multiple of that power to add to make that digit
roll to 0, but my first guess is that this very likely will cost us more
than the at most 16 cycles to wrap it (needing a number of base-k
multiplies), so better just punt and just add 17^n repeatedly to do it.

If you have only 1 unit, then you could get more complicated skip logic
and let the other bases inject their skips, but you need to be careful
about not lettin yourself add too much and go past the roll over point
as after a skip you might not be at the right nmultiple of the power of
thqt base. The question becomes if it is worth the complexity.

```
Reply by May 10, 20212021-05-10
```Richard Damon <Richard@Damon-Family.org> schrieb:
> I suppose the big question is how big of gaps do you tend to find, If it
> can jumps thousands of values, it could well be worth it, and I suppose
> it well could be. I could see the binary represtation could establish an
> upper bound for the sum of digits, and if higher order digits of some
> base exceed that value, you know you need to increment till those
> change, which could be a very big jump.

You are right, the gaps are indeed huge, and the gains enormous.

If I limit myself to 72 bits, I have around 4.72237E+21 possible
binary numbers, but "only" 2.91386E+18 eligible numbers base 17 which
have a sum of digits of 72 or less, so this is a reduction by
a factor of 1600 alone, more if you look at the actual ranges
rather than the maximum as I did above.  For base 13, the factor
is around 120, for 11 it is 50.
```
Reply by May 9, 20212021-05-09
```On 5/9/21 5:21 PM, Nelson Ribeiro wrote:
>  I agree with you Richard. I did not thought of that!
>  Its definitely a very efficient way to process like 200M 72-bit numbers per second (assuming 200MHz in a cheap modern FPGA device with some pipelining) with one small FPGA engine/coprocessor.
>

My guess is that that would be the processing rate for a single core
unit, which will take about 2k Luts.

Reasonable cheap FPGAs will likely handle a small multiple of that.

Maybe getting 10s of copies in middle sized but still reasonably priced.

This does assume that you will be just incrementing through the values.

IF you are able to skip large jumps, that might help you with a
different algorithm, and perhaps that would be worth it. If it is just
occational jumps of large values, perhaps giving up some number of
processors to have a unit that can compute the next possible value and
factor into the needed bases, and then restart there.

I suppose the big question is how big of gaps do you tend to find, If it
can jumps thousands of values, it could well be worth it, and I suppose
it well could be. I could see the binary represtation could establish an
upper bound for the sum of digits, and if higher order digits of some
base exceed that value, you know you need to increment till those
change, which could be a very big jump.
```
Reply by May 9, 20212021-05-09
``` I agree with you Richard. I did not thought of that!
Its definitely a very efficient way to process like 200M 72-bit numbers per second (assuming 200MHz in a cheap modern FPGA device with some pipelining) with one small FPGA engine/coprocessor.
```
Reply by May 9, 20212021-05-09
```On 5/9/21 4:21 PM, Thomas Koenig wrote:
> Nelson Ribeiro <ngrr.ribeiro@gmail.com> schrieb:
>
>> If I understood you correctly, what you want would be an FPGA
>> engine/coprocessor that you make the equivalent calculations
>> of the na&iuml;ve C code that I have below. That is a pretty neat
>> mathematical problem!
>
> Yep, it's neat.  What I did worked for all primes up to 13,
> but 17 is just too far off (so far).
>
>> I hope that you know a more efficient way of converting any number
>> to a sequence of digits of a given base than the one I have written.
>
> In the immortal words of Henry S. Warren of "Hacker's Delight"
> fame: "On many computers, division is very time consuming and is
> to be avoided when possible."
>
> He also gives a neat bag of tricks of calculating the division
> remainder of many odd constants, by selectively summing their
> digits.  This works for numbers n where
>
> 2 ^ m = 1 (mod n)
>
> so you can break your number into chunks of m bits, add them
> together and still have the same remainder.
>
> Once you have calculated the remainder by repeated addition of
> these chunks to a size you can manage, you can then divide by
> multiplying with the modular inverse of its number.
>
> This will give you a single digit of your base n number, to
> be repeated until the number has been converted to base n.
> For base three, 4 = 3+1, so any grouping of bits with
> an even number works.
>
> I understand most FPGAs have six-bit lookup tables these days.
> For calculating the remainder base three, that is actually
> pretty handy - use 12*2 LUTs to reduce the bits from 72
> to 24 in one go.  Repeat, and you are left with 8 bits,
> which is definitely managable.
>
> Of course, then comes the 72*72 bit multiplication, which is
> probably going to take some time...
>
> Base 11 and 13 are less friendly, they would need 10 respectively
> 12 bit lookup tables.
>
>> For "convertBase(m, 2);  sum1 = SumArray();" you can use a
>> pipelined 'popcount' arquitecture,
>
> That is one thing I already looked at.  There is a rather
> elegant popcnt implementation using a 6-bit counter.
>

Unless the problem has something I am overlooking, there is no reason to
try to convert an 'aarbirary' number into the various bases.

If you start with the representation of the number X in these bases, it
is very simple to compute X+N in all the bases for a fixed number N. By
starting with N consecutive numbers precomputed in the bases (like the
numbers 1 to N), you would then step through all numbers above that
until some base overflows its storage.

No need for big multipliers or dividers, just simple constant
incrementers. For example, for the base 17 digits, represented with 5
bits, you just need the current 5 bit, the 1 bit carry in, and 5
CONSTANT increment value, so it is simple lookup for each bit. Maybe to
do a bit of work to optimize the carry chain for speed.
```
Reply by May 9, 20212021-05-09
```Richard Damon <Richard@Damon-Family.org> schrieb:

> My thought was to build a series of 'Base-X' counters/accumulators, in
> the bases, 2, 3, 5, 7, 11, 13, 17. This is a fairly simple operation,
> especially since the increment value will be a constant equal to the
> number copies of the system. Start with them all at the same value (like
> 0) and just increment them by the same value expressed in their base.

That sounds like a good possibility.

There is one important thing: It is possible to reduce the
amount of work done rather dramatically, and this is also
necessary.

Going to 2^64 with this problem (which I have already done) means
looking at around 1.84e19 numbers.  Running at 500e6 Hz and doing
one test per cycle would lead to 3.7e10 seconds running time,
or about 1170 years.  Too long.

The serial version of the code consists of nested loops running from
0 to 16.  The sum of digits reached so far is easy to calculate,
just add the sum of the digits to the new one.  The minimum number
of digits base 17 then is that sum.

It is then possible to calculate the maximum number of bits that the
binary representation in that range can have, and skip the loop
if that is too large.

Example: If the sum of the first five leading digits base 17 is 85,
there is no way that we will find a number with 72 bits whose
popcount is equal to 85.

That has saved a _lot_ of computing effort, at the cost of adding
some complexity to the program.

So, any counter will have to have some rather complicated logic
to make it skip the values where there cannot possibly be a match.
```
Reply by May 9, 20212021-05-09
```Nelson Ribeiro <ngrr.ribeiro@gmail.com> schrieb:

> If I understood you correctly, what you want would be an FPGA
> engine/coprocessor that you make the equivalent calculations
> of the na&iuml;ve C code that I have below. That is a pretty neat
> mathematical problem!

Yep, it's neat.  What I did worked for all primes up to 13,
but 17 is just too far off (so far).

> I hope that you know a more efficient way of converting any number
> to a sequence of digits of a given base than the one I have written.

In the immortal words of Henry S. Warren of "Hacker's Delight"
fame: "On many computers, division is very time consuming and is
to be avoided when possible."

He also gives a neat bag of tricks of calculating the division
remainder of many odd constants, by selectively summing their
digits.  This works for numbers n where

2 ^ m = 1 (mod n)

so you can break your number into chunks of m bits, add them
together and still have the same remainder.

Once you have calculated the remainder by repeated addition of
these chunks to a size you can manage, you can then divide by
multiplying with the modular inverse of its number.

This will give you a single digit of your base n number, to
be repeated until the number has been converted to base n.
For base three, 4 = 3+1, so any grouping of bits with
an even number works.

I understand most FPGAs have six-bit lookup tables these days.
For calculating the remainder base three, that is actually
pretty handy - use 12*2 LUTs to reduce the bits from 72
to 24 in one go.  Repeat, and you are left with 8 bits,
which is definitely managable.

Of course, then comes the 72*72 bit multiplication, which is
probably going to take some time...

Base 11 and 13 are less friendly, they would need 10 respectively
12 bit lookup tables.

> For "convertBase(m, 2);  sum1 = SumArray();" you can use a
> pipelined 'popcount' arquitecture,

That is one thing I already looked at.  There is a rather
elegant popcnt implementation using a 6-bit counter.
```
Reply by May 9, 20212021-05-09
```On 5/9/21 2:21 PM, Nelson Ribeiro wrote:
> Hi Thomas.
>
> If I understood you correctly, what you want would be an FPGA engine/coprocessor that you make the equivalent calculations of the na&iuml;ve C code that I have below. That is a pretty neat mathematical problem!
> I hope that you know a more efficient way of converting any number to a sequence of digits of a given base than the one I have written.
> The convertBase() algorithm that I wrote is not exactly FPGA friendly, but it can be managed to put in a FPGA in a efficient way with Dividers and Multipliers in pipeline maybe...
>
> My advice is to find some metrics that you want for a first smallish FPGA engine/coprocessor (like process 10M numbers per second, using up 2000LUTS, 500FFs, 2BRAMs, 4 mults 18x18). Any FPGA board should be good to start this project, but for a beginner it is better to use some streamline board. Then, it is a matter of replicating that FPGA engine/coprocessor and how much money you can afford in buying a board with big FPGA device or some cloud time in some FPGA cloud server. And it is possible that something that you can put to work at 100MHz in a cheap FPGA board, may run at 400MHz in a very expensive one...
>
> For "convertBase(m, 2);  sum1 = SumArray();" you can use a pipelined 'popcount' arquitecture, for the other cases you may use  pipelined tree adders (with a small numbers of bits this will be really fast).  With pipeline, you can execute the section "SumArray();" as if it was being execute it in just one clock cycle at 100MHz or 200MHz or even more!
>
> The not so FPGA friendly part is really the "convertBase()" algorithm. That loop with a division (and a multiplication) is a bit troublesome... I hope you know better algorithm to perform this part. I can think in ways of using pipelined dividers... but most likely it is not the most efficient way...
>
> Regards,
> Nelson
>
>

I would NOT do a convertBase() type archtecture for the FPGA. It is just
too unfriendly.

My thought was to build a series of 'Base-X' counters/accumulators, in
the bases, 2, 3, 5, 7, 11, 13, 17. This is a fairly simple operation,
especially since the increment value will be a constant equal to the
number copies of the system. Start with them all at the same value (like
0) and just increment them by the same value expressed in their base.

This becomes an easy one cycle to update system.
```