On Wednesday, June 23, 2021 at 1:42:41 AM UTC-7, Anssi Saari wrote:
> Tianxiang Weng <wtx...@gmail.com> writes: 
> 
> > I now ha another similar problem: how to change an integer to a std_logic_vector. 
> > 
> > Here is a code snippet: 
> > signal X :integer range 0 to 15; 
> > signal Y :
> Maybe save a copy of this: 
> 
> https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf 
> 
> It has pretty good coverage on type conversions in VHDL.

Hi,
Thank you. 
When I opened the *.pdf file and planned to save it, a surprising thing happened: my computer has already had a copy of it. After downloading it, I never read it. Its name is "DRAFT Standard for Floating-Point Arithmetic P754-Draft 129", I thought it is for Floating-Point Arithmetic only, and I never use Floating-Point Arithmetic in VHDL. After your post, I changed the pdf file name to "VHDL-Type conversion".

This time I will read it carefully.

Weng

Tianxiang Weng <wtxwtx@gmail.com> writes:

> I now ha another similar problem: how to change an integer to a std_logic_vector.
>
> Here is a code snippet:
> signal X :integer range 0 to 15;
> signal Y :

Maybe save a copy of this:

https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

It has pretty good coverage on type conversions in VHDL.

On Tuesday, June 22, 2021 at 3:27:40 AM UTC-7, Tianxiang Weng wrote:
> On Tuesday, June 22, 2021 at 3:18:18 AM UTC-7, Tianxiang Weng wrote: 
> > On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote: 
> > > On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote: 
> > > > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1); 
> > > andrew_b, thank you!!! 
> > > 
> > > Weng 
> Hi,
> I now have another similar problem: how to change an integer to a std_logic_vector.in VHDL-2002.
> Here is a code snippet:
> signal X :integer range 0 to 15; -- X is used as an index to an array. 
> signal Y :std_logic_vector(3 downto 0); -- Y is a device input interface so Y data type cannot change, but X may be. 
> 
> Y <= std_logic_vector(X); -- error! 
> 
> Thank you. 
> 
> Weng

Hi,
In https://groups.google.com/g/comp.arch.fpga/c/vkeCNxzCvdc/m/wOk5AZVR0ksJ, I learned the solution:
Y <= std_logic_vector(to_unsigned(X, WIDTH)); 

Thank you.

Weng

On Tuesday, June 22, 2021 at 3:18:18 AM UTC-7, Tianxiang Weng wrote:
> On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote: 
> > On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote: 
> > > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1); 
> > andrew_b, thank you!!! 
> > 
> > Weng
Hi, 
I now have another similar problem: how to change an integer to a std_logic_vector.in VHDL-2002.

Here is a code snippet: 

signal X :integer range 0 to 15;                 -- X is used as an index to an array.
signal Y :std_logic_vector(3 downto 0);  -- Y is a device input interface so Y data type cannot change, but X may be.

Y <= std_logic_vector(X);  -- error!

Thank you.

Weng 

On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote:
> On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote: 
> > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);
> andrew_b, thank you!!! 
> 
> Weng

Hi,
I now ha another similar problem: how to change an integer to a std_logic_vector.

Here is a code snippet:
signal X :integer range 0 to 15;
signal Y :

On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);

andrew_b, thank you!!!

Weng

Series_Number <= std_logic_vector (unsigned (Series_Number) + 1); 

> Series_Number <= Series_Number+std_logic_vector(unsigned(Series_Number)+1); 
> Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);

Hi,
It is a long time headache for me to increase a data of std_logic_vector by 1.

Here are examples:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

constant ONE : std_logic_vector(7 downto 0);
signal   Series_Number : std_logic_vector(7 downto 0);
...
All followings generate errors in VHDL-2002:
Series_Number <= Series_Number +1;
Series_Number <= Series_Number +'1';
Series_Number <= Series_Number+std_logic_vector(unsigned(Series_Number)+1);
Series_Number <= Series_Number+ONE;

Thank you. 

Weng