> Roger,
>
> There is not a way to directly view the GSR signal within a design
> but there is a pseudo-way to get it. If you instantiate an FD, and tie
> the input to Vcc and connect your clock, the FF will reset to zero when
> GSR is asserted and go to one the first clock cycle GSR is deasserted.
> You can invert the polarity by setting the INIT attribute to a one and
> tying a ground to the input. You may need to place some attributes on
> the FF to make sure the tools do not optimize it away thinking it is a
> constant but in theory, that should give to a look at to when GSR is
> asserted for the rest of your design. I would not know whey you would
> every try to build memory within and FPGA out of LUTs configured as nand
> and inv gates when you can have much more efficient use of the LUTs when
> configured as memories but to each their own.
>
I do not actually plan to build memory elements in the FPGA. I only
cited as a possible academic situation where one migth require the
FPGA's gsr signal.
In regard to your proposd idea: Great idea! It needs a clock and as
such the oscillator startup time is added to the gsr pulse, but that
does not matter. Until the clock shows up, the gsr can be asserted or
negated --> gsr being held or released will will have no impact if
there is no clock! Thx!
-Roger
Reply by Brian Philofsky●April 10, 20062006-04-10
Roger,
There is not a way to directly view the GSR signal within a design
but there is a pseudo-way to get it. If you instantiate an FD, and tie
the input to Vcc and connect your clock, the FF will reset to zero when
GSR is asserted and go to one the first clock cycle GSR is deasserted.
You can invert the polarity by setting the INIT attribute to a one and
tying a ground to the input. You may need to place some attributes on
the FF to make sure the tools do not optimize it away thinking it is a
constant but in theory, that should give to a look at to when GSR is
asserted for the rest of your design. I would not know whey you would
every try to build memory within and FPGA out of LUTs configured as nand
and inv gates when you can have much more efficient use of the LUTs when
configured as memories but to each their own.
-- Brian
Roger Bourne wrote:
>
> What I meant by the above was:
> Is there a way to insert the FPGA's GSR net in a shematic design?
>
> The reason I was asking the question was because I was thinking about
> the situation were nand & inv gates are used to constructed a bulky
> (and slow) memory element. (If such a construction is permitted in an
> fpga) . In that situation, the fpga's gsr net would come in handy for
> the memory's element initialization.
>
> -Roger
>
Reply by Roger Bourne●April 7, 20062006-04-07
> > However, If I wanted to access the fpga's self-generating internal gsr
> > net for initialization purposes of let's say a custom-made logic cell
> > in which there is memory (in other words, feedbacking an even number of
> > inverting-logic cells.... Actually, I do not if feedback is possible
> > for fpgas (it was always possible in asics...)), how would I then
> > invoke the fpga's self-generating internal gsr net?
>
> I'm not sure what you mean here. The GSR network is automatically
> pulsed at the end of configuration. Your FPGA design can also assert
> GSR by driving the GSR input to the STARTUP_SPARTAN3 primitive.
>
What I meant by the above was:
Is there a way to insert the FPGA's GSR net in a shematic design?
The reason I was asking the question was because I was thinking about
the situation were nand & inv gates are used to constructed a bulky
(and slow) memory element. (If such a construction is permitted in an
fpga) . In that situation, the fpga's gsr net would come in handy for
the memory's element initialization.
-Roger
Reply by Steve Knapp (Xilinx Spartan-3 Generation FPGAs)●April 7, 20062006-04-07
Roger Bourne wrote:
> > The GSR input then essentially provides a "stealth" connection to every
> > flip-flop within the FPGA. No further connections are required. You
> > still have a second independent control to individual flip-flop via the
> > set/reset inputs.
> >
>
> I think I see. All the FFs (and similar modules that require resets or
> presets) in the FPGA are ALREADY connected to a secondary unshown gsr
> network. This is the fpga's self-generating internal gsr network that
> the fpga provides upon power-on. All FFs have additionnaly a second
> user-accessible async. reset or preset that can be simply grounded if
> not used. Right ?
Correct. BTW, if you are using schematic capture, there are also
flip-flop primitives without set or reset, which saves you from tying
off unused inputs.
> However, If I wanted to access the fpga's self-generating internal gsr
> net for initialization purposes of let's say a custom-made logic cell
> in which there is memory (in other words, feedbacking an even number of
> inverting-logic cells.... Actually, I do not if feedback is possible
> for fpgas (it was always possible in asics...)), how would I then
> invoke the fpga's self-generating internal gsr net?
I'm not sure what you mean here. The GSR network is automatically
pulsed at the end of configuration. Your FPGA design can also assert
GSR by driving the GSR input to the STARTUP_SPARTAN3 primitive.
> Also I tried to find the fpga's self-generating internal gsr net in a
> modelsim simulation. Alas no cigar. Would it be possible to visualize
> the fpga's self-generating internal gsr net during simulation?
> The GSR input then essentially provides a "stealth" connection to every
> flip-flop within the FPGA. No further connections are required. You
> still have a second independent control to individual flip-flop via the
> set/reset inputs.
>
I think I see. All the FFs (and similar modules that require resets or
presets) in the FPGA are ALREADY connected to a secondary unshown gsr
network. This is the fpga's self-generating internal gsr network that
the fpga provides upon power-on. All FFs have additionnaly a second
user-accessible async. reset or preset that can be simply grounded if
not used. Right ?
However, If I wanted to access the fpga's self-generating internal gsr
net for initialization purposes of let's say a custom-made logic cell
in which there is memory (in other words, feedbacking an even number of
inverting-logic cells.... Actually, I do not if feedback is possible
for fpgas (it was always possible in asics...)), how would I then
invoke the fpga's self-generating internal gsr net?
Also I tried to find the fpga's self-generating internal gsr net in a
modelsim simulation. Alas no cigar. Would it be possible to visualize
the fpga's self-generating internal gsr net during simulation?
Thx in advance for all your help.
-Roger
Reply by Steve Knapp (Xilinx Spartan-3 Generation FPGAs)●April 7, 20062006-04-07
Roger Bourne wrote:
> Roger Bourne wrote:
[ ... snip ...]
> When I inserted the STARTUP_SPARTAN3 module in the top level schematic,
> and connected it's GSR pin to the top level schematic's GSR net, I
> obtained the following message:
>
> Warning:DesignEntry - toplevel_schem.sch: Net 'GSR' is connected to
> load pins and/or I/O markers, but not connected to any source pin or
> I/O marker.
> Totally, 1 error(s) and warning(s) are detected
>
> It seems that the STARTUP_SPARTAN3 module cannot drive its GSR pin. Is
> its GSR pin an input or an output ?
> Are there any options I need to set?
I believe the software is attempting to tell you that the GSR signal
has one or more loads connected (likely the GSR input) but there is
nothing driving it (no pin or internal logic). The GSR connection on
the STARTUP_SPARTAN3 primitive is an input and requires a driving
signal.
The GSR input then essentially provides a "stealth" connection to every
flip-flop within the FPGA. No further connections are required. You
still have a second independent control to individual flip-flop via the
set/reset inputs.
BTW, the GSR (Global Set/Reset) function can save quite a bit of logic
when migrating a design from an ASIC. In an ASIC, you need a global
connection to all the flip-flops to place them in a pre-defined state.
In the FPGA, the flip-flops are automatically set/reset (depending on
the flip-flop primitive used) at the very end of configuration, just
before your FPGA applications starts operating. Furthermore, you can
set/reset all the flip-flops at any time via the GSR input.
If you are interested, Ken Chapman has a good article (as always) on
the topic at ...
Get Smart About Reset (Think Local, Not Global)
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=kc_smart_reset
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
Reply by Roger Bourne●April 7, 20062006-04-07
Roger Bourne wrote:
> Errrr...
>
> When I typed the previous post, I did not have access to the project
> navigator software...
> So...
>
> > I had tried that before but I was confused as the STARTUP_SPARTAN3
> > module had both GSRin and GSRout pins. I had assumed that the module
> > was only for simulation purposes.
> > ( At least I think it was the STARTUP_SPARTAN3 module. There were only
> > 2 modules that had began with the wotd "startup", and I had tried them
> > both. They were identical.)
>
> Today, (that I have access to the projects navigator software) I took a
> closer look at both modules that began with the word "startup". I
> realized that both modules are in fact NOT the same. I was able to
> locate the 3 pin STARTUP_SPARTAN3 module. ( I was previously selecting
> the STARBUF_SPARTAN3 module. Spelling is too similar).
>
> Thank you for your help.
> -Roger
Hmmm...
When I inserted the STARTUP_SPARTAN3 module in the top level schematic,
and connected it's GSR pin to the top level schematic's GSR net, I
obtained the following message:
Warning:DesignEntry - toplevel_schem.sch: Net 'GSR' is connected to
load pins and/or I/O markers, but not connected to any source pin or
I/O marker.
Totally, 1 error(s) and warning(s) are detected
It seems that the STARTUP_SPARTAN3 module cannot drive its GSR pin. Is
its GSR pin an input or an output ?
Are there any options I need to set?
Please advise
-Roger
Reply by Roger Bourne●April 7, 20062006-04-07
Errrr...
When I typed the previous post, I did not have access to the project
navigator software...
So...
> I had tried that before but I was confused as the STARTUP_SPARTAN3
> module had both GSRin and GSRout pins. I had assumed that the module
> was only for simulation purposes.
> ( At least I think it was the STARTUP_SPARTAN3 module. There were only
> 2 modules that had began with the wotd "startup", and I had tried them
> both. They were identical.)
Today, (that I have access to the projects navigator software) I took a
closer look at both modules that began with the word "startup". I
realized that both modules are in fact NOT the same. I was able to
locate the 3 pin STARTUP_SPARTAN3 module. ( I was previously selecting
the STARBUF_SPARTAN3 module. Spelling is too similar).
Thank you for your help.
-Roger
Reply by Roger Bourne●April 6, 20062006-04-06
>Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
> Hi Roger,
>
> Roger Bourne wrote:
> > Hello all,
> >
> > I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE
> > Project navigator to design the FPGA). My question is the following:
> >
> > In schematic edition, to make a net take on the property of the GSR
> > net, do you simply just rename it to "GSR"? or does it have to be
> > tapped from a module ? or is the GSR net always tapped from an IO pad?
> > I tried it (it==remaming it to "GSR") and the schematic editor just
> > sees it as any other net.
> > The datasheet refers to a global GSR network, but does explain how do
> > the knitty-gritty...I.E if the net has to be named "glbl.gsr" or some
> > other reserved name.
> >
> > Please advise
> > -Roger Bourne
>
> The GSR signal connects to a design element called a STARTUP_SPARTAN3.
> There is a description on PDF page 1,097 in the Libraries Guide.
> http://toolbox.xilinx.com/docsan/xilinx8/books/docs/lib/lib.pdf
>
> For the schematic editor, just look for the symbol called
> STARTUP_SPARTAN3.
>
> For HDLs, you would need to instantiate the STARTUP_SPARTAN3 primitive
> and then connect to it.
>
> Sorry for the confusion.
>
> ---------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> General Products Division
> Spartan-3/-3E FPGAs
> http://www.xilinx.com/spartan3e
> ---------------------------------
> The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
Thank you Steve.
I had tried that before but I was confused as the STARTUP_SPARTAN3
module had both GSRin and GSRout pins. I had assumed that the module
was only for simulation purposes.
( At least I think it was the STARTUP_SPARTAN3 module. There were only
2 modules that had began with the wotd "startup", and I had tried them
both. They were identical.)
....
So just to be clear, if I were to tap the GSR signal from the GSRout
pin of the STARTUP_SPARTAN3 module AND leave the GSRin pin floating,
will the FPGA will generate a GSR signal ?
P.S. The symbol of the STARTUP_SPARTAN3 module drawn in the datasheet
does not resemble the one obtained from the symbol library. The one in
the datasheet has 3 pins as opposed to the one from the symbol library
has 5 pins.
Please advise
-Roger
Reply by Steve Knapp (Xilinx Spartan-3 Generation FPGAs)●April 6, 20062006-04-06
Hi Roger,
Roger Bourne wrote:
> Hello all,
>
> I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE
> Project navigator to design the FPGA). My question is the following:
>
> In schematic edition, to make a net take on the property of the GSR
> net, do you simply just rename it to "GSR"? or does it have to be
> tapped from a module ? or is the GSR net always tapped from an IO pad?
> I tried it (it==remaming it to "GSR") and the schematic editor just
> sees it as any other net.
> The datasheet refers to a global GSR network, but does explain how do
> the knitty-gritty...I.E if the net has to be named "glbl.gsr" or some
> other reserved name.
>
> Please advise
> -Roger Bourne
The GSR signal connects to a design element called a STARTUP_SPARTAN3.
There is a description on PDF page 1,097 in the Libraries Guide.
http://toolbox.xilinx.com/docsan/xilinx8/books/docs/lib/lib.pdf
For the schematic editor, just look for the symbol called
STARTUP_SPARTAN3.
For HDLs, you would need to instantiate the STARTUP_SPARTAN3 primitive
and then connect to it.
Sorry for the confusion.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.