Hi,

I'm looking for a VHDL example code to implement a DDR memory in a Altera
'Stratix'.
(not a controler), with use of RAS, CAS, etc...
There is many example of memory in Megawizard of Quartus (DP-RAM, FIFO), but
I can't find DDR.

I would like to have this DDR include in specific memory block (M-RAM or
M512 or others).

Thanks for your help,

bhb