Reply by March 9, 20072007-03-09
John McCaskill wrote:
> After all, hafnium is only half as good as unobtanium
Sure, but it's considerably less than half as expensive.
Reply by Paul March 9, 20072007-03-09
"I personally see the FPGAs following a road that leads them to
looking a
 lot like microcontrollers but with FPGA fabric where the processor
is."

....  Wrong way around... FPGA fabric where the controllers are, hard
silicon where the processor is... and they've already done this...
virtex FX series parts - powerPC in hard silicon, runs the speed of a
power pc in hard silicon (fast) surrounded by FPGA fabric that you can
do whatever you need to with....



On Mar 7, 2:01 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> I personally see the FPGAs following a road that leads them to looking a > lot like microcontrollers but with FPGA fabric where the processor is. > > ---Matthew Hicks > > > > > Hi, > > I just got a newsletter stating the Spartan3AN being available now. > > While > > these Spartan3AN are market as "new non-volatile" FPGAs, this might > > (IMHO) > > be misleading. For my understanding "non-volatile" would mean no > > configuration on power-ON (as e.g. ACTEL AntiFuse) rather than > > Config-Eprom > > being integrated in FPGA chip's housing (being a separate die as > > well). > > Nevertheless this definitely is a nice appraoch, saving space and > > copper > > traces on PCB. > > As always, as soon as the new chip is on market the question on next > > enhancements arises. Any truth in rumors stating next generation > > Spartan (or > > what it will be called) has integrated Analog-Digital Converters? > > CU, Carlhermann Schlehaus- Hide quoted text - > > - Show quoted text -
Reply by John McCaskill March 9, 20072007-03-09
On Mar 8, 10:51 am, "Symon" <symon_bre...@hotmail.com> wrote:
> "John McCaskill" <junkm...@fastertechnology.com> wrote in message > > news:1173371757.756269.53650@h3g2000cwc.googlegroups.com... > > > On Mar 8, 10:06 am, Austin Lesea <aus...@xilinx.com> wrote: > >> Symon, > > >> Intel is keeping this secret. If true, it is a huge improvement, and > >> one that the foundries will be itching to get their hands on. > > >> The hi-K dielectric for the transistor will keep the roadmap moving > >> forward with lower leakage (the gates leak at 65nm and below), and > >> perhaps better speed (hi-K makes the transistor stronger according to > >> Intel). > > >> Austin > > > I don't remember where I first saw it mentioned, but they are not > > keeping it a secret. Here are a few mentions about it: > > >http://pubs.acs.org/cen/news/85/i06/8506notw4.html > >http://www.intel.com/technology/silicon/45nm_technology.htm > > > And here is the leading supplier of it: > > >http://www.wahchang.com/pages/products/data/hafnium.htm > > > Regards, > > > John McCaskill > >www.fastertechnology.com > > I guess Austin means they're keeping the process details secret, not the > results. Go to the above link you posted on intel.com and search for > 'secret'! ;-) > HTH, Syms.
Perhaps that is what he meant, but I would expect that either Intel would licence their technology after a while, or the IBM/AMD/Sony/ Toshiba group will. If none of them want to license it, I didn't want it anyway. After all, hafnium is only half as good as unobtanium which is used in all the best -K dielectrics. Regards, John McCaskill www.fastertechnology.com
Reply by Jim Granville March 8, 20072007-03-08
Andy Peters wrote:
> I do recall certain Xilinx representatives saying something like "on- > board configuration memory means that we'll have to use an older > process, meaning slower, more power-hungry parts, yadda yadda > yadda."
That was refering to same-die configuration; the process constraints go away then you deploy 2 die in one package, which is what Xilinx have done. Some companies simply wire bond the second die in a spare area, in BGA that's easy - just design the BGA paddle & pgm the bonding machine. Others are working on flip-chip bump bonding, where the die is designed to take the daughter chip, and the bonding costs drop (not just $, but area/height costs too ) and you can get a lot of contacts going between the die. If you are already doing flip-chip onto the BGA, to get die-wide bond pads, and lower nH, then it's somewhat harder to find a place to put the second memory die ..... -jg
Reply by Andy Peters March 8, 20072007-03-08
On Mar 7, 11:47 am, "news.t-online.de" <carlhermann.schleh...@t-
online.de> wrote:
> I just got a newsletter stating the Spartan3AN being available now. While > these Spartan3AN are market as "new non-volatile" FPGAs, this might (IMHO) > be misleading. For my understanding "non-volatile" would mean no > configuration on power-ON (as e.g. ACTEL AntiFuse) rather than Config-Eprom > being integrated in FPGA chip's housing (being a separate die as well). > Nevertheless this definitely is a nice appraoch, saving space and copper > traces on PCB.
The parts aren't "available now." (We'd like to see the smaller 3A parts ...) Anyways, the Lattice XP devices, which have been around for quite awhile, have built-in configuration flash memory and start up a lot quicker than the 3AN devices. I haven't done a detailed side-by-side feature comparison, but it looks like one Xilinx advantage is that their flash can be used for both configuration and as part of the design; the Lattice memory is for configuration only. I dunno who's faster, who's got more resources, who's less expensive, etc. I do recall certain Xilinx representatives saying something like "on- board configuration memory means that we'll have to use an older process, meaning slower, more power-hungry parts, yadda yadda yadda." -a
Reply by Brian Drummond March 8, 20072007-03-08
On 7 Mar 2007 11:27:14 -0800, "Peter Alfke" <peter@xilinx.com> wrote:

>Without divulging any secrets (hell,I do not even work in that >division of Xilinx, so how would I know?): >The biggest problem in integrating an A/D converter is deciding on its >parameters. >Should it be a slow, high-precision sigma-delta type, or successive >approximation, or a fast flash converter? Single channel or multi- >channel? >The trouble is that these are irreversible decision. You cannot morph >a slow 12-bit converter into a fast 8-bit converter (like you do >easily in the digital domain).
For a delta-sigma converter, I don't believe this is true. Its hardware is fundamentally a very fast, low-resolution (typically 1-bit!) ADC, coupled to a similar DAC, via an n'th order filter in a feedback loop to perform noise-shaping, ie to shift quantisation noise out of the desired frequency band into another part of the spectrum. This has to be followed by a band-limiting filter (in the digital domain), normally accompanied by decimation to the sample rate of interest. The dumbest implementation, a first order high pass filter in the feedback loop, is recognisable as an integrator - but typically a third order filter is employed. Now it's been a long time since I read Bob Adams' papers, but reading between the lines it seemed obvious that you could choose the noise-shaping filter to suit your application, selecting different ones for extremely low noise in a narrow bandwidth, or higher noise levels in a wider band, the product of the two parameters being roughly constant. The bandlimiting/decimation filter obviously has to track this choice. (Selecting between filters is safer than full programmability, a poor choice of filter in a feedback loop leads to instability!) - Brian
Reply by Symon March 8, 20072007-03-08
"John McCaskill" <junkmail@fastertechnology.com> wrote in message 
news:1173371757.756269.53650@h3g2000cwc.googlegroups.com...
> On Mar 8, 10:06 am, Austin Lesea <aus...@xilinx.com> wrote: >> Symon, >> >> Intel is keeping this secret. If true, it is a huge improvement, and >> one that the foundries will be itching to get their hands on. >> >> The hi-K dielectric for the transistor will keep the roadmap moving >> forward with lower leakage (the gates leak at 65nm and below), and >> perhaps better speed (hi-K makes the transistor stronger according to >> Intel). >> >> Austin > > I don't remember where I first saw it mentioned, but they are not > keeping it a secret. Here are a few mentions about it: > > http://pubs.acs.org/cen/news/85/i06/8506notw4.html > http://www.intel.com/technology/silicon/45nm_technology.htm > > And here is the leading supplier of it: > > http://www.wahchang.com/pages/products/data/hafnium.htm > > Regards, > > John McCaskill > www.fastertechnology.com >
I guess Austin means they're keeping the process details secret, not the results. Go to the above link you posted on intel.com and search for 'secret'! ;-) HTH, Syms.
Reply by John McCaskill March 8, 20072007-03-08
On Mar 8, 10:06 am, Austin Lesea <aus...@xilinx.com> wrote:
> Symon, > > Intel is keeping this secret. If true, it is a huge improvement, and > one that the foundries will be itching to get their hands on. > > The hi-K dielectric for the transistor will keep the roadmap moving > forward with lower leakage (the gates leak at 65nm and below), and > perhaps better speed (hi-K makes the transistor stronger according to > Intel). > > Austin
I don't remember where I first saw it mentioned, but they are not keeping it a secret. Here are a few mentions about it: http://pubs.acs.org/cen/news/85/i06/8506notw4.html http://www.intel.com/technology/silicon/45nm_technology.htm And here is the leading supplier of it: http://www.wahchang.com/pages/products/data/hafnium.htm Regards, John McCaskill www.fastertechnology.com
Reply by Austin Lesea March 8, 20072007-03-08
Symon,

Intel is keeping this secret.  If true, it is a huge improvement, and
one that the foundries will be itching to get their hands on.

The hi-K dielectric for the transistor will keep the roadmap moving
forward with lower leakage (the gates leak at 65nm and below), and
perhaps better speed (hi-K makes the transistor stronger according to
Intel).

Austin

Reply by dalai lamah March 8, 20072007-03-08
Un bel giorno Jim Granville digit&#2013265922;:

> Most of the FPGA architectures I know of, all load the config : I'm not > sure even anti-fuse devices have the fuses actually in the signal path. > (imagine the tpd cost, of those fuse-program circuits ! )
Actually I think that Actel antifuse FPGAs are made that way (otherwise it wouldn't make much sense to differentiate between "flash" and "antifuse" FPGAs, like Actel does). See for example http://www.actel.com/documents/RTAXS_DS.pdf, page 7 and following. I agree with the OP, in my opinion defining S3AN as "nonvolatile" is quite inaccurate. Maybe it isn't misleading for an engineer (it's very clear, starting from the name, that the S3AN is just the usual SRAM device with a boot flash embedded), but it could be misleading for a IT manager that takes decisions about things he doesn't know (i.e. the 95% of the grand total). -- emboliaschizoide.splinder.com