Paul wrote:
> Hi
> 
> I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a 
> Instruction width of 6 bits. I have a design for which I had 
> automatically generated a JTAG Controller. I can successfully sythesize 
> the design as well as the JTAG TAP. The problem is just that when I use 
> ChipScope Pro with to connect to the device it tells me that there are 0
> Core units found in the JTAG device chain.
> 
> I have the following options when generating the JTAG TAP Controller:
> 
> Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
> Version Number: 0
> Pert Number:     0
> Manufacturer:    0
> TDI Signal name: tdi
> TDO Signal name: tdo
> TMS Signal name: tms
> TCK Signal name: tck
> TRST Signal name: trst_n
> 
> I dont think that Version number, Part Number and Manufacturer are 
> critical, right? Anyone an idea what I could have been missing?
> Probably something obvious when running the synthesis with Xilinx XST?
> 
> Many thanks for helpful tips!
> Paul

It sounds like you created your own unique JTAG TAP controller for some
reason and put it in your design and expect that ChipScope would work
with it.  It won't.

ChipScope uses the built in JTAG controller to communicate through the
internal BSCAN block and one of the internal USER ports to a soft ICON
(Integrated CONtroller) core and then to 1-15 ChipScope debug cores
such as ILA (Integrated Logic Analyzer) or VIO (Virtual Input/Output).

I would strongly suggest that you read the introduction chapter in the
ChipScope 7.1i User Guide for a better understanding of using ChipScope.
http://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_7_1i_ug029.pdf

Ed McGettigan
--
Xilinx Inc.

On Dec 11, 8:03 pm, Paul <P...@yahoo.co.uk> wrote:
> Hi
>
> I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a
> Instruction width of 6 bits. I have a design for which I had
> automatically generated a JTAG Controller. I can successfully sythesize
> the design as well as the JTAG TAP. The problem is just that when I use
> ChipScope Pro with to connect to the device it tells me that there are 0
> Core units found in the JTAG device chain.

for chipscope connection to the fpga, you need JTAG, but you can use
it only when you're sure of working your JTAG controller properly.
Also if you need to monitor this controller or any other design, you
need to add your demanded signals to chipscope core. if a JTAG port is
selected to connect to FPGA that dosn't have any apropriate core on
the chip(fpga) then you will receive this report:  "There are 0 Core
units found in the JTAG device chain."
make sure you add and generate your monitoring chipscope core to your
design.

AHN

Paul wrote:
> Hi
> 
> I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a
> Instruction width of 6 bits. I have a design for which I had
> automatically generated a JTAG Controller. I can successfully sythesize
> the design as well as the JTAG TAP. The problem is just that when I use
> ChipScope Pro with to connect to the device it tells me that there are 0
> Core units found in the JTAG device chain.
> 
> I have the following options when generating the JTAG TAP Controller:
> 
> Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
> Version Number: 0
> Pert Number:     0
> Manufacturer:    0
> TDI Signal name: tdi
> TDO Signal name: tdo
> TMS Signal name: tms
> TCK Signal name: tck
> TRST Signal name: trst_n
> 
> I dont think that Version number, Part Number and Manufacturer are
> critical, right? Anyone an idea what I could have been missing?
> Probably something obvious when running the synthesis with Xilinx XST?
> 
> Many thanks for helpful tips!
> Paul

Hi,

  In order to debug the basic connectivity, I would insert or
instantiate a ICON/ILA or ICON/VIO and see how that works.

  I've seen that 0 cores found problem when the generated core is newer
than the Chipscope version.

  Also, the trst_n shown is active low, is that intended for the TAP
controller?

HTH,
-P@

Hi

I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a 
Instruction width of 6 bits. I have a design for which I had 
automatically generated a JTAG Controller. I can successfully sythesize 
the design as well as the JTAG TAP. The problem is just that when I use 
ChipScope Pro with to connect to the device it tells me that there are 0
Core units found in the JTAG device chain.

I have the following options when generating the JTAG TAP Controller:

Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
Version Number: 0
Pert Number: 	0
Manufacturer:	0
TDI Signal name: tdi
TDO Signal name: tdo
TMS Signal name: tms
TCK Signal name: tck
TRST Signal name: trst_n

I dont think that Version number, Part Number and Manufacturer are 
critical, right? Anyone an idea what I could have been missing?
Probably something obvious when running the synthesis with Xilinx XST?

Many thanks for helpful tips!
Paul