On Jun 5, 7:15=A0am, muthu...@gmail.com wrote:
> Hello,
>
> I have 2 boards, of which one has PPC core and other do not.
>
> [board1 /w PPC]-------uart-------[board2 /wo PPC]
>
> I want to use UART as a debug interface for board2.
>
> So,I am looking for a UART Master core that shall be Maser on the PLB/
> OPB bus that I can use it in board2 FPGA.
>
> The Xilinx EDK library provide UART cores that has PLB/OPB interfaces
> as core side interfaces. But these interfaces are Slave interface.
>
> Do anyone has UART core (Master on PLB/OPB)? Is it advisable to go for
> such setup?
>
> Thank you.
>
> Best regards,
> Muthu

Hi Muthu,

I do not know if this is the best way to go, this depends on your
application requirements. A UART would be a slow way to control the
bus on the second board but it may be enough.
I also needed something like that mainly for debugging or controlling
configuration register from a PC. So, I wrote a small interpreter
connected to a UART that can control a BUS in the FPGA. Its not PLB/
OPB compatible but can be modified as required. The interpreter can
receive either ASCII commands from a PC Terminal for example or binary
format commands which are much more efficient and also support block
reading/writing.
If you think it might help you please send me an email and I will send
you the source files.

Regards,
Moti

Hello,

I have 2 boards, of which one has PPC core and other do not.

[board1 /w PPC]-------uart-------[board2 /wo PPC]

I want to use UART as a debug interface for board2.

So,I am looking for a UART Master core that shall be Maser on the PLB/
OPB bus that I can use it in board2 FPGA.

The Xilinx EDK library provide UART cores that has PLB/OPB interfaces
as core side interfaces. But these interfaces are Slave interface.

Do anyone has UART core (Master on PLB/OPB)? Is it advisable to go for
such setup?

Thank you.

Best regards,
Muthu