"woko" <wkopp@gmx.net> wrote in message 
news:f5eda5fe-e895-4b72-8894-5a96007bdc58@d77g2000hsb.googlegroups.com...
> On 8 Sep., 18:59, "Symon" <symon_bre...@hotmail.com> wrote:
>
>
> Hi Symon,
> I had a look at XAPP224 and XAPP250 (for a recovered clock). At this
> state I think we can not fully replace the LV1023A and LV1224B for the
> full speed.
> Because we transmit the signal over cable the input sensitivity could
> also be an issue. I read that the FPGA inputs have more input capacity
> than dedicated LVDS inputs.
> The transmitter at relative low speed (24Mhz clock; 288Mbs) would be
> possible, I think.
>
> Thanks for your answers!
>
> Best regards,
>
> Wolfgang
>
Hi Wolfgang,
Agreed, if your data rate is over 500Mbps, I think you need to use the 
external serdes solution or maybe RocketI/O as the other poster suggested.If 
you had double the LVDS channels, so half the rate, then you would probably 
be able to do it in the FPGA.
Cheers, Syms.

On 8 Sep., 18:59, "Symon" <symon_bre...@hotmail.com> wrote:
> "woko" <wk...@gmx.net> wrote in message
>
> news:4d1085f3-8c9d-4f56-8966-976446092be8@x41g2000hsb.googlegroups.com...
>
> > HiFPGAspecialist,
>
> > we are would like to know if it is currently possible to implement
> > high speedLVDSreceiver or transmitter in FPGAs.
>
> > Our next gerneration PCB board would have about 12LVDSreceiver
> > (SN65LV1224B) , 6LVDS transmitter (SN65LV1023A) and anFPGA
> > onboard.
> > Please note that the LV1224 and LV1023 transmit thairLVDSin a single
> > differential line, there is noLVDSclock pair necessary. The clock
> > speed would be 48Mhz which would lead to aLVDSbandwidth of 576Mbs
> > (12bit transmitting).
> > It would save us money andFPGAIOs if we could get the serialization
> > and deserialization  in theFPGA.
>
> > I could find application notes aboutLVDSin a cyclone3, but I don't
> > think that reception works without a clock pair.
>
> > Is anybody out there which as experience with this kind ofLVDSin a
> >FPGA?
> > We would be obliged for some practical hits...
>
> > Curious about your answers,
> > Wolfgang Kopp
>
> Hi Wolfgang,
> Data recovery without a clock is easy at 48Mbps. STW for XAPP224.
> HTH., Syms.


Hi Symon,
I had a look at XAPP224 and XAPP250 (for a recovered clock). At this
state I think we can not fully replace the LV1023A and LV1224B for the
full speed.
Because we transmit the signal over cable the input sensitivity could
also be an issue. I read that the FPGA inputs have more input capacity
than dedicated LVDS inputs.
The transmitter at relative low speed (24Mhz clock; 288Mbs) would be
possible, I think.

Thanks for your answers!

Best regards,

Wolfgang

"woko" <wkopp@gmx.net> wrote in message 
news:4d1085f3-8c9d-4f56-8966-976446092be8@x41g2000hsb.googlegroups.com...
> Hi FPGA specialist,
>
> we are would like to know if it is currently possible to implement
> high speed LVDS receiver or transmitter in FPGAs.
>
> Our next gerneration PCB board would have about 12 LVDS receiver
> (SN65LV1224B) , 6 LVDS  transmitter (SN65LV1023A) and an FPGA
> onboard.
> Please note that the LV1224 and LV1023 transmit thair LVDS in a single
> differential line, there is no LVDS clock pair necessary. The clock
> speed would be 48Mhz which would lead to a LVDS bandwidth of 576Mbs
> (12bit transmitting).
> It would save us money and FPGA IOs if we could get the serialization
> and deserialization  in the FPGA.
>
> I could find application notes about LVDS in a cyclone3, but I don't
> think that reception works without a clock pair.
>
> Is anybody out there which as experience with this kind of LVDS in a
> FPGA?
> We would be obliged for some practical hits...
>
>
> Curious about your answers,
> Wolfgang Kopp
>
Hi Wolfgang,
Data recovery without a clock is easy at 48Mbps. STW for XAPP224.
HTH., Syms. 

I'm currently working on a board with two Virtex-5
parts running LVDS IO between the two FPGAs.  The interface
between the FPGAs is 23 pairs of LVDS, with a source
synchronous clock.  This is using a modified version
of the ChipSync logic documented in XAPP860.  The LVDS
IO is running DDR at 500MHz giving 1Gbs per pair, or 23 Gbps
total.

We also have an interface running at 644MHz, but that
is not yet tested.

I haven't looked at running without a source sync clock,
but it should be possible if you are willing to put in
a method to adjust the delay on either the clock, or each of
the data pairs (IDELAY + logic).  Again look at XAPP860.

If you need clock recovery, the look at the Xilinx parts
with RocketIO.


woko wrote:
> Hi FPGA specialist,
> 
> we are would like to know if it is currently possible to implement
> high speed LVDS receiver or transmitter in FPGAs.
> 
> Our next gerneration PCB board would have about 12 LVDS receiver
> (SN65LV1224B) , 6 LVDS  transmitter (SN65LV1023A) and an FPGA
> onboard.
> Please note that the LV1224 and LV1023 transmit thair LVDS in a single
> differential line, there is no LVDS clock pair necessary. The clock
> speed would be 48Mhz which would lead to a LVDS bandwidth of 576Mbs
> (12bit transmitting).
> It would save us money and FPGA IOs if we could get the serialization
> and deserialization  in the FPGA.
> 
> I could find application notes about LVDS in a cyclone3, but I don't
> think that reception works without a clock pair.
> 
> Is anybody out there which as experience with this kind of LVDS in a
> FPGA?
> We would be obliged for some practical hits...
> 
> 
> Curious about your answers,
> Wolfgang Kopp
> 
> 
> 

Hi FPGA specialist,

we are would like to know if it is currently possible to implement
high speed LVDS receiver or transmitter in FPGAs.

Our next gerneration PCB board would have about 12 LVDS receiver
(SN65LV1224B) , 6 LVDS  transmitter (SN65LV1023A) and an FPGA
onboard.
Please note that the LV1224 and LV1023 transmit thair LVDS in a single
differential line, there is no LVDS clock pair necessary. The clock
speed would be 48Mhz which would lead to a LVDS bandwidth of 576Mbs
(12bit transmitting).
It would save us money and FPGA IOs if we could get the serialization
and deserialization  in the FPGA.

I could find application notes about LVDS in a cyclone3, but I don't
think that reception works without a clock pair.

Is anybody out there which as experience with this kind of LVDS in a
FPGA?
We would be obliged for some practical hits...


Curious about your answers,
Wolfgang Kopp