Reply by simax October 29, 20082008-10-29
ok ....i did that ...but im having the same proble as before... the
model says "# ** Warning: Invalid start of initialization
#    Time: 6939100 ps  Iteration: 5  Instance: /system_test/ddr1/
behavior"

the only different thing is the time he says that...

i think its an option in mpmc but i dont know which of these
thousands....
Reply by simax October 29, 20082008-10-29
hello,
i run it for 1 ms... atm i changed some code of the ddr modul which
made that the initialization of the ddr modul happens after the mpmc
tried to ...
but i=B4ll try yours too...

cheers
Reply by Jim Wu October 29, 20082008-10-29
How long did you run the simulation? You can open the wrapper file for
MPMC, then search for C_SKIP_SIM_INIT_DELAY and check what value it is
set to. If it is set to 0, there will be very long delay (>200us)
before MPMC can start DDR2 SDRAM initialization. You should set it to
1 for simulation, which you can do it manually or set it from MPMC GUI
(under Advanced tab and then Misc tab) in EDK.

Cheers,
Jim


On Oct 29, 12:01=A0pm, simax <opitz.fr...@googlemail.com> wrote:
> Hello > > Im trying to simulate the MPMC with an DDR2 Memory. Ive got the > problem that the mpmc wont initialise the ddr2 modul. The > Idelayctrl_Rdy_I is 1 but it wont talk to the memory. Im using the > mt47h64m16 memory modul from freemodelfoundry. > > My mpmc is instantiated =A0with : > > BEGIN mpmc > =A0PARAMETER INSTANCE =3D mpmc_0 > =A0PARAMETER HW_VER =3D 4.03.a > =A0PARAMETER C_MEM_PARTNO =3D MT47H64M16-3 > =A0PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000 > =A0PARAMETER C_PIM1_BASETYPE =3D 4 > =A0PARAMETER C_NUM_PORTS =3D 2 > =A0PARAMETER C_MPMC_BASEADDR =3D 0xA0000000 > =A0PARAMETER C_MPMC_HIGHADDR =3D 0xAFFFFFFF > =A0PARAMETER C_MEM_DATA_WIDTH =3D 32 > =A0BUS_INTERFACE SPLB0 =3D mb_plb > =A0PORT MPMC_Clk90 =3D clk_125_90 > =A0PORT MPMC_Clk_200MHz =3D clk_200_0 > =A0PORT MPMC_Clk0 =3D sys_clk_s > =A0PORT MPMC_Rst =3D sys_rst_s > =A0PORT DDR2_DQS_n =3D mpmc_0_DDR2_DQS_n > =A0PORT DDR2_DQS =3D mpmc_0_DDR2_DQS > =A0PORT DDR2_DM =3D mpmc_0_DDR2_DM > =A0PORT DDR2_DQ =3D mpmc_0_DDR2_DQ > =A0PORT DDR2_Addr =3D mpmc_0_DDR2_Addr > =A0PORT DDR2_BankAddr =3D mpmc_0_DDR2_BankAddr > =A0PORT DDR2_WE_n =3D mpmc_0_DDR2_WE_n > =A0PORT DDR2_CAS_n =3D mpmc_0_DDR2_CAS_n > =A0PORT DDR2_RAS_n =3D mpmc_0_DDR2_RAS_n > =A0PORT DDR2_ODT =3D mpmc_0_DDR2_ODT > =A0PORT DDR2_CS_n =3D mpmc_0_DDR2_CS_n > =A0PORT DDR2_CE =3D mpmc_0_DDR2_CE > =A0PORT DDR2_Clk_n =3D mpmc_0_DDR2_Clk_n > =A0PORT DDR2_Clk =3D mpmc_0_DDR2_Clk > =A0PORT PIM1_InitDone =3D mpmc_0_PIM1_InitDone > =A0PORT PIM1_RdFIFO_Latency =3D mpmc_0_PIM1_RdFIFO_Latency > =A0PORT PIM1_RdFIFO_Flush =3D mpmc_0_PIM1_RdFIFO_Flush > =A0PORT PIM1_RdFIFO_Empty =3D mpmc_0_PIM1_RdFIFO_Empty > =A0PORT PIM1_WrFIFO_Flush =3D mpmc_0_PIM1_WrFIFO_Flush > =A0PORT PIM1_WrFIFO_AlmostFull =3D mpmc_0_PIM1_WrFIFO_AlmostFull > =A0PORT PIM1_WrFIFO_Empty =3D mpmc_0_PIM1_WrFIFO_Empty > =A0PORT PIM1_RdFIFO_RdWdAddr =3D mpmc_0_PIM1_RdFIFO_RdWdAddr > =A0PORT PIM1_RdFIFO_Pop =3D mpmc_0_PIM1_RdFIFO_Pop > =A0PORT PIM1_RdFIFO_Data =3D mpmc_0_PIM1_RdFIFO_Data > =A0PORT PIM1_WrFIFO_Push =3D mpmc_0_PIM1_WrFIFO_Push > =A0PORT PIM1_WrFIFO_BE =3D mpmc_0_PIM1_WrFIFO_BE > =A0PORT PIM1_WrFIFO_Data =3D mpmc_0_PIM1_WrFIFO_Data > =A0PORT PIM1_RdModWr =3D mpmc_0_PIM1_RdModWr > =A0PORT PIM1_Size =3D mpmc_0_PIM1_Size > =A0PORT PIM1_RNW =3D mpmc_0_PIM1_RNW > =A0PORT PIM1_AddrAck =3D mpmc_0_PIM1_AddrAck > =A0PORT PIM1_AddrReq =3D mpmc_0_PIM1_AddrReq > =A0PORT PIM1_Addr =3D mpmc_0_PIM1_Addr > END > > and i connected them in a test file (see bottom of this post...) > > =A0Please help me and tell me what is missing or wrong... > > thx > > #################################################################### > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > USE IEEE.VITAL_timing.ALL; > USE IEEE.VITAL_primitives.ALL; > USE STD.textio.ALL; > > library UNISIM; > use UNISIM.VCOMPONENTS.ALL; > > LIBRARY FMF; =A0 =A0 =A0 USE FMF.gen_utils.ALL; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0USE FMF.conversions.ALL; > > entity system_test is > end system_test; > > architecture test of system_test is > > component system is > =A0 port ( > =A0 =A0 fpga_0_LEDS_GPIO_d_out_pin : out std_logic_vector(0 to 31); > =A0 =A0 sys_clk_pin : in std_logic; > =A0 =A0 sys_rst_pin : in std_logic; > =A0 =A0 mpmc_0_DDR2_DQS_n : inout std_logic_vector(3 downto 0); > =A0 =A0 mpmc_0_DDR2_DQS : inout std_logic_vector(3 downto 0); > =A0 =A0 mpmc_0_DDR2_DM_pin : out std_logic_vector(3 downto 0); > =A0 =A0 mpmc_0_DDR2_DQ : inout std_logic_vector(31 downto 0); > =A0 =A0 mpmc_0_DDR2_Addr_pin : out std_logic_vector(12 downto 0); > =A0 =A0 mpmc_0_DDR2_BankAddr_pin : out std_logic_vector(2 downto 0); > =A0 =A0 mpmc_0_DDR2_WE_n_pin : out std_logic; > =A0 =A0 mpmc_0_DDR2_CAS_n_pin : out std_logic; > =A0 =A0 mpmc_0_DDR2_RAS_n_pin : out std_logic; > =A0 =A0 mpmc_0_DDR2_ODT_pin : out std_logic_vector(0 to 0); > =A0 =A0 mpmc_0_DDR2_CS_n_pin : out std_logic_vector(0 to 0); > =A0 =A0 mpmc_0_DDR2_CE_pin : out std_logic_vector(0 to 0); > =A0 =A0 mpmc_0_DDR2_Clk_n_pin : out std_logic_vector(0 to 0); > =A0 =A0 mpmc_0_DDR2_Clk_pin : out std_logic_vector(0 to 0); > =A0 =A0 mpmc_0_PIM1_InitDone_pin : out std_logic; > =A0 =A0 mpmc_0_PIM1_RdFIFO_Latency_pin : out std_logic_vector(1 downto 0)=
;
> =A0 =A0 mpmc_0_PIM1_RdFIFO_Flush_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_RdFIFO_Empty_pin : out std_logic; > =A0 =A0 mpmc_0_PIM1_WrFIFO_Flush_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_WrFIFO_AlmostFull_pin : out std_logic; > =A0 =A0 mpmc_0_PIM1_WrFIFO_Empty_pin : out std_logic; > =A0 =A0 mpmc_0_PIM1_RdFIFO_RdWdAddr_pin : out std_logic_vector(3 downto > 0); > =A0 =A0 mpmc_0_PIM1_RdFIFO_Pop_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_RdFIFO_Data_pin : out std_logic_vector(63 downto 0); > =A0 =A0 mpmc_0_PIM1_WrFIFO_Push_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_WrFIFO_BE_pin : in std_logic_vector(7 downto 0); > =A0 =A0 mpmc_0_PIM1_WrFIFO_Data_pin : in std_logic_vector(63 downto 0); > =A0 =A0 mpmc_0_PIM1_RdModWr_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_Size_pin : in std_logic_vector(3 downto 0); > =A0 =A0 mpmc_0_PIM1_RNW_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_AddrAck_pin : out std_logic; > =A0 =A0 mpmc_0_PIM1_AddrReq_pin : in std_logic; > =A0 =A0 mpmc_0_PIM1_Addr_pin : in std_logic_vector(31 downto 0) > =A0 ); > end component; > > component mt47h64m16 IS > =A0 =A0 GENERIC ( > =A0 =A0 =A0 =A0 -- tipd delays: interconnect path delays > =A0 =A0 =A0 =A0 tipd_ODT =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_CK =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_CKNeg =A0 =A0 =A0 =A0: VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_CKE =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_CSNeg =A0 =A0 =A0 =A0: VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_RASNeg =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZero=
Delay01;
> =A0 =A0 =A0 =A0 tipd_CASNeg =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZero=
Delay01;
> =A0 =A0 =A0 =A0 tipd_WENeg =A0 =A0 =A0 =A0: VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_LDM =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_UDM =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_BA0 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_BA1 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_BA2 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A0 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A1 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A2 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A3 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A4 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A5 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A6 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A7 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A8 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A9 =A0 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A10 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A11 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_A12 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ0 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ1 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ2 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ3 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ4 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ5 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ6 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ7 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ8 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ9 =A0 =A0 =A0 =A0 =A0: VitalDelayType01 :=3D Vital=
ZeroDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ10 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ11 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ12 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ13 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ14 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_DQ15 =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_UDQS =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_UDQSNeg =A0 =A0 =A0: VitalDelayType01 :=3D VitalZero=
Delay01;
> =A0 =A0 =A0 =A0 tipd_LDQS =A0 =A0 =A0 =A0 : VitalDelayType01 :=3D VitalZe=
roDelay01;
> =A0 =A0 =A0 =A0 tipd_LDQSNeg =A0 =A0 =A0: VitalDelayType01 :=3D VitalZero=
Delay01;
> > =A0 =A0 =A0 =A0 -- tpd delays > =A0 =A0 =A0 =A0 tpd_CK_DQ0 =A0 =A0 =A0 =A0: VitalDelayType01Z :=3D UnitDe=
lay01Z; --
> tAC(max), tHZ > =A0 =A0 =A0 =A0 tpd_CK_DQ1 =A0 =A0 =A0 =A0: VitalDelayType :=3D UnitDelay=
; -- tAC(min)
> =A0 =A0 =A0 =A0 tpd_CK_LDQS =A0 =A0 =A0 : VitalDelayType01Z :=3D UnitDela=
y01Z; --
> tDQSCK(max) > > =A0 =A0 =A0 =A0 -- tsetup values > =A0 =A0 =A0 =A0 tsetup_DQ0_LDQS =A0 : VitalDelayType :=3D UnitDelay; -- t=
DSb
> =A0 =A0 =A0 =A0 tsetup_A0_CK =A0 =A0 =A0: VitalDelayType :=3D UnitDelay; =
-- tISb
> =A0 =A0 =A0 =A0 tsetup_LDQS_CK_CL3_negedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDSS > =A0 =A0 =A0 =A0 tsetup_LDQS_CK_CL4_negedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDSS > =A0 =A0 =A0 =A0 tsetup_LDQS_CK_CL5_negedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDSS > =A0 =A0 =A0 =A0 tsetup_LDQS_CK_CL6_negedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDSS > > =A0 =A0 =A0 =A0 -- thold values > =A0 =A0 =A0 =A0 thold_DQ0_LDQS =A0 =A0: VitalDelayType :=3D UnitDelay; --=
tDHb
> =A0 =A0 =A0 =A0 thold_A0_CK =A0 =A0 =A0 : VitalDelayType :=3D UnitDelay; =
-- tIHb
> =A0 =A0 =A0 =A0 thold_LDQS_CK_CL3_posedge_posedge : VitalDelayType :=3D > UnitDelay; -- tDSH > =A0 =A0 =A0 =A0 thold_LDQS_CK_CL4_posedge_posedge : VitalDelayType :=3D > UnitDelay; -- tDSH > =A0 =A0 =A0 =A0 thold_LDQS_CK_CL5_posedge_posedge : VitalDelayType :=3D > UnitDelay; -- tDSH > =A0 =A0 =A0 =A0 thold_LDQS_CK_CL6_posedge_posedge : VitalDelayType :=3D > UnitDelay; -- tDSH > > =A0 =A0 =A0 =A0 -- tpw values > =A0 =A0 =A0 =A0 tpw_CK_CL3_posedge: VitalDelayType :=3D UnitDelay; -- tCH=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL3_negedge: VitalDelayType :=3D UnitDelay; -- tCL=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL4_posedge: VitalDelayType :=3D UnitDelay; -- tCH=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL4_negedge: VitalDelayType :=3D UnitDelay; -- tCL=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL5_posedge: VitalDelayType :=3D UnitDelay; -- tCH=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL5_negedge: VitalDelayType :=3D UnitDelay; -- tCL=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL6_posedge: VitalDelayType :=3D UnitDelay; -- tCH=
AVG
> =A0 =A0 =A0 =A0 tpw_CK_CL6_negedge: VitalDelayType :=3D UnitDelay; -- tCL=
AVG
> =A0 =A0 =A0 =A0 tpw_A0_CL3 =A0 =A0 =A0 =A0: VitalDelayType :=3D UnitDelay=
; -- tIPW
> =A0 =A0 =A0 =A0 tpw_A0_CL4 =A0 =A0 =A0 =A0: VitalDelayType :=3D UnitDelay=
; -- tIPW
> =A0 =A0 =A0 =A0 tpw_A0_CL5 =A0 =A0 =A0 =A0: VitalDelayType :=3D UnitDelay=
; -- tIPW
> =A0 =A0 =A0 =A0 tpw_A0_CL6 =A0 =A0 =A0 =A0: VitalDelayType :=3D UnitDelay=
; -- tIPW
> =A0 =A0 =A0 =A0 tpw_DQ0_CL3 =A0 =A0 =A0 : VitalDelayType :=3D UnitDelay; =
-- tDIPW
> =A0 =A0 =A0 =A0 tpw_DQ0_CL4 =A0 =A0 =A0 : VitalDelayType :=3D UnitDelay; =
-- tDIPW
> =A0 =A0 =A0 =A0 tpw_DQ0_CL5 =A0 =A0 =A0 : VitalDelayType :=3D UnitDelay; =
-- tDIPW
> =A0 =A0 =A0 =A0 tpw_DQ0_CL6 =A0 =A0 =A0 : VitalDelayType :=3D UnitDelay; =
-- tDIPW
> =A0 =A0 =A0 =A0 tpw_LDQS_normCL3_posedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSH > =A0 =A0 =A0 =A0 tpw_LDQS_normCL3_negedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSL > =A0 =A0 =A0 =A0 tpw_LDQS_normCL4_posedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSH > =A0 =A0 =A0 =A0 tpw_LDQS_normCL4_negedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSL > =A0 =A0 =A0 =A0 tpw_LDQS_normCL5_posedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSH > =A0 =A0 =A0 =A0 tpw_LDQS_normCL5_negedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSL > =A0 =A0 =A0 =A0 tpw_LDQS_normCL6_posedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSH > =A0 =A0 =A0 =A0 tpw_LDQS_normCL6_negedge : VitalDelayType :=3D UnitDelay;=
--
> tDQSL > =A0 =A0 =A0 =A0 tpw_LDQS_preCL3_negedge =A0: VitalDelayType :=3D UnitDela=
y; --
> tWPRE > =A0 =A0 =A0 =A0 tpw_LDQS_preCL4_negedge =A0: VitalDelayType :=3D UnitDela=
y; --
> tWPRE > =A0 =A0 =A0 =A0 tpw_LDQS_preCL5_negedge =A0: VitalDelayType :=3D UnitDela=
y; --
> tWPRE > =A0 =A0 =A0 =A0 tpw_LDQS_preCL6_negedge =A0: VitalDelayType :=3D UnitDela=
y; --
> tWPRE > =A0 =A0 =A0 =A0 tpw_LDQS_postCL3_negedge : VitalDelayType :=3D UnitDelay;=
--
> tWPST > =A0 =A0 =A0 =A0 tpw_LDQS_postCL4_negedge : VitalDelayType :=3D UnitDelay;=
--
> tWPST > =A0 =A0 =A0 =A0 tpw_LDQS_postCL5_negedge : VitalDelayType :=3D UnitDelay;=
--
> tWPST > =A0 =A0 =A0 =A0 tpw_LDQS_postCL6_negedge : VitalDelayType :=3D UnitDelay;=
--
> tWPST > > =A0 =A0 =A0 =A0 -- tperiod values > =A0 =A0 =A0 =A0 tperiod_CK_CL3 =A0 =A0: VitalDelayType :=3D UnitDelay; -- > tCKAVG(min) > =A0 =A0 =A0 =A0 tperiod_CK_CL4 =A0 =A0: VitalDelayType :=3D UnitDelay; -- > tCKAVG(min) > =A0 =A0 =A0 =A0 tperiod_CK_CL5 =A0 =A0: VitalDelayType :=3D UnitDelay; -- > tCKAVG(min) > =A0 =A0 =A0 =A0 tperiod_CK_CL6 =A0 =A0: VitalDelayType :=3D UnitDelay; -- > tCKAVG(min) > > =A0 =A0 =A0 =A0 -- tskew values > =A0 =A0 =A0 =A0 tskew_CK_LDQS_CL3_posedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDQSS > =A0 =A0 =A0 =A0 tskew_CK_LDQS_CL4_posedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDQSS > =A0 =A0 =A0 =A0 tskew_CK_LDQS_CL5_posedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDQSS > =A0 =A0 =A0 =A0 tskew_CK_LDQS_CL6_posedge_posedge: VitalDelayType :=3D > UnitDelay; -- tDQSS > > =A0 =A0 =A0 =A0 -- tdevice values: values for internal delays > =A0 =A0 =A0 =A0 tdevice_tRC =A0 =A0 =A0 : VitalDelayType =A0 =A0:=3D 54 n=
s; -- tRC
> =A0 =A0 =A0 =A0 tdevice_tRRD =A0 =A0 =A0: VitalDelayType =A0 =A0:=3D 10 n=
s; -- tRRD
> =A0 =A0 =A0 =A0 tdevice_tRCD =A0 =A0 =A0: VitalDelayType =A0 =A0:=3D 12 n=
s; -- tRCD
> =A0 =A0 =A0 =A0 tdevice_tFAW =A0 =A0 =A0: VitalDelayType =A0 =A0:=3D 50 n=
s; -- tFAW
> =A0 =A0 =A0 =A0 tdevice_tRASMIN =A0 : VitalDelayType =A0 =A0:=3D 40 ns; -=
- tRAS(min)
> =A0 =A0 =A0 =A0 tdevice_tRASMAX =A0 : VitalDelayType =A0 =A0:=3D 70 us; -=
- tRAS(max)
> =A0 =A0 =A0 =A0 tdevice_tRTP =A0 =A0 =A0: VitalDelayType =A0 =A0:=3D 7.5 =
ns; -- tRTP
> =A0 =A0 =A0 =A0 tdevice_tWR =A0 =A0 =A0 : VitalDelayType =A0 =A0:=3D 15 n=
s; -- tWR
> =A0 =A0 =A0 =A0 tdevice_tWTR =A0 =A0 =A0: VitalDelayType =A0 =A0:=3D 7.5 =
ns; -- tWTR
> =A0 =A0 =A0 =A0 tdevice_tRP =A0 =A0 =A0 : VitalDelayType =A0 =A0:=3D 12 n=
s; -- tRP
> =A0 =A0 =A0 =A0 tdevice_tRFCMIN =A0 : VitalDelayType =A0 =A0:=3D 127.5 ns=
; --
> tRFC(min) > =A0 =A0 =A0 =A0 tdevice_tRFCMAX =A0 : VitalDelayType =A0 =A0:=3D 70 us; -=
- tRFC(max)
> =A0 =A0 =A0 =A0 tdevice_REFPer =A0 =A0: VitalDelayType =A0 =A0:=3D 64 ms;=
-- refresh
> period > =A0 =A0 =A0 =A0 tdevice_tCKAVGMAX : VitalDelayType =A0 =A0:=3D 8 ns; -- t=
CKAVG(max)
> > =A0 =A0 =A0 =A0 -- generic control parameters > =A0 =A0 =A0 =A0 InstancePath =A0 =A0 =A0: string =A0 =A0:=3D DefaultInsta=
ncePath;
> =A0 =A0 =A0 =A0 TimingChecksOn =A0 =A0: boolean =A0 :=3D DefaultTimingChe=
cks;
> =A0 =A0 =A0 =A0 MsgOn =A0 =A0 =A0 =A0 =A0 =A0 : boolean =A0 :=3D DefaultM=
sgOn;
> =A0 =A0 =A0 =A0 XOn =A0 =A0 =A0 =A0 =A0 =A0 =A0 : boolean =A0 :=3D Defaul=
tXon;
> > =A0 =A0 =A0 =A0 -- memory file to be loaded > =A0 =A0 =A0 =A0 mem_file_name =A0 =A0 : string =A0 =A0:=3D "none"; > =A0 =A0 =A0 =A0 UserPreload =A0 =A0 =A0 : boolean =A0 :=3D FALSE; > > =A0 =A0 =A0 =A0 -- For FMF SDF technology file usage > =A0 =A0 =A0 =A0 TimingModel =A0 =A0 =A0 : string =A0 =A0:=3D DefaultTimin=
gModel
> =A0 =A0 ); > =A0 =A0 PORT ( > =A0 =A0 =A0 =A0 ODT =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 CK =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 CKNeg =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D 'U'=
;
> =A0 =A0 =A0 =A0 CKE =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 CSNeg =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D 'U'=
;
> =A0 =A0 =A0 =A0 RASNeg =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D 'U'=
;
> =A0 =A0 =A0 =A0 CASNeg =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D 'U'=
;
> =A0 =A0 =A0 =A0 WENeg =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D 'U'=
;
> =A0 =A0 =A0 =A0 LDM =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 UDM =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 BA0 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 BA1 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 BA2 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A1 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A2 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A3 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A4 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A5 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A6 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A7 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A8 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A9 =A0 =A0 =A0 =A0 =A0 =A0 =A0: IN =A0 =A0std_ulogic :=3D=
'U';
> =A0 =A0 =A0 =A0 A10 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 A11 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 A12 =A0 =A0 =A0 =A0 =A0 =A0 : IN =A0 =A0std_ulogic :=3D '=
U';
> =A0 =A0 =A0 =A0 DQ0 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ1 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ2 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ3 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ4 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ5 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ6 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ7 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ8 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ9 =A0 =A0 =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ10 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ11 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ12 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ13 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ14 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 DQ15 =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 UDQS =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 UDQSNeg =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 LDQS =A0 =A0 =A0 =A0 =A0 =A0: INOUT std_ulogic :=3D 'U'; > =A0 =A0 =A0 =A0 LDQSNeg =A0 =A0 =A0 =A0 : INOUT std_ulogic :=3D 'U' > =A0 =A0 ); > > END component; > > signal fpga_0_LEDS_GPIO_d_out_pin : std_logic_vector(0 to 31); > signal sys_clk_pin : =A0std_logic :=3D'0'; > signal sys_rst_pin : =A0std_logic :=3D'0'; > signal test_DDR2_DQS_n : =A0std_logic_vector(3 downto 0); > signal test_DDR2_DQS : =A0std_logic_vector(3 downto 0); > signal test_DDR2_DM_pin : =A0std_logic_vector(3 downto 0); > signal test_DDR2_DQ : =A0std_logic_vector(31 downto 0); > signal test_DDR2_Addr_pin : =A0std_logic_vector(12 downto 0); > signal test_DDR2_BankAddr_pin : =A0std_logic_vector(2 downto 0); > signal test_DDR2_WE_n_pin : =A0std_logic; > signal test_DDR2_CAS_n_pin : =A0std_logic; > signal test_DDR2_RAS_n_pin : =A0std_logic; > signal test_DDR2_ODT_pin : =A0std_logic_vector(0 to 0); > signal test_DDR2_CS_n_pin : =A0std_logic_vector(0 to 0); > signal test_DDR2_CE_pin : =A0std_logic_vector(0 to 0); > signal test_DDR2_Clk_n_pin : =A0std_logic_vector(0 to 0); > signal test_DDR2_Clk_pin : =A0std_logic_vector(0 to 0); > signal test_PIM1_InitDone_pin : =A0std_logic; > signal test_PIM1_RdFIFO_Latency_pin : =A0std_logic_vector(1 downto 0); > signal test_PIM1_RdFIFO_Flush_pin : =A0std_logic:=3D'0'; > signal test_PIM1_RdFIFO_Empty_pin : =A0std_logic; > signal test_PIM1_WrFIFO_Flush_pin : =A0std_logic:=3D'0'; > signal test_PIM1_WrFIFO_AlmostFull_pin : =A0std_logic; > signal test_PIM1_WrFIFO_Empty_pin : =A0std_logic; > signal test_PIM1_RdFIFO_RdWdAddr_pin : =A0std_logic_vector(3 downto > 0):=3D(others =3D>'0'); > signal test_PIM1_RdFIFO_Pop_pin : =A0std_logic:=3D'0'; > signal test_PIM1_RdFIFO_Data_pin : =A0std_logic_vector(63 downto > 0):=3D(others =3D>'0'); > signal test_PIM1_WrFIFO_Push_pin : =A0std_logic:=3D'0'; > signal test_PIM1_WrFIFO_BE_pin : =A0std_logic_vector(7 downto > 0):=3D(others =3D>'0'); > signal test_PIM1_WrFIFO_Data_pin : =A0std_logic_vector(63 downto > 0):=3D(others =3D>'0'); > signal test_PIM1_RdModWr_pin : =A0std_logic:=3D'0'; > signal test_PIM1_Size_pin : =A0std_logic_vector(3 downto 0):=3D(others > =3D>'0'); > signal test_PIM1_RNW_pin : =A0std_logic:=3D'0'; > signal test_PIM1_AddrAck_pin : =A0std_logic :=3D'0'; > signal test_PIM1_AddrReq_pin : =A0std_logic:=3D'0'; > signal test_PIM1_Addr_pin : =A0std_logic_vector(31 downto 0):=3D(others > =3D>'0'); > > begin > > dut: system > =A0 port map ( > =A0 =A0 fpga_0_LEDS_GPIO_d_out_pin =3D>fpga_0_LEDS_GPIO_d_out_pin, > =A0 =A0 sys_clk_pin =3D> sys_clk_pin, > =A0 =A0 sys_rst_pin =3D> sys_rst_pin, > =A0 =A0 mpmc_0_DDR2_DQS_n =3D> test_DDR2_DQS_n, > =A0 =A0 mpmc_0_DDR2_DQS =3D> test_DDR2_DQS, > =A0 =A0 mpmc_0_DDR2_DM_pin =3D> test_DDR2_DM_pin, > =A0 =A0 mpmc_0_DDR2_DQ =3D> test_DDR2_DQ, > =A0 =A0 mpmc_0_DDR2_Addr_pin =3D> test_DDR2_Addr_pin, > =A0 =A0 mpmc_0_DDR2_BankAddr_pin =3D> test_DDR2_BankAddr_pin, > =A0 =A0 mpmc_0_DDR2_WE_n_pin =3D> test_DDR2_WE_n_pin, > =A0 =A0 mpmc_0_DDR2_CAS_n_pin =3D> test_DDR2_CAS_n_pin, > =A0 =A0 mpmc_0_DDR2_RAS_n_pin =3D> test_DDR2_RAS_n_pin, > =A0 =A0 mpmc_0_DDR2_ODT_pin =3D> test_DDR2_ODT_pin, > =A0 =A0 mpmc_0_DDR2_CS_n_pin =3D> test_DDR2_CS_n_pin, > =A0 =A0 mpmc_0_DDR2_CE_pin =3D> test_DDR2_CE_pin, > =A0 =A0 mpmc_0_DDR2_Clk_n_pin =3D> test_DDR2_Clk_n_pin, > =A0 =A0 mpmc_0_DDR2_Clk_pin =3D> test_DDR2_Clk_pin, > =A0 =A0 mpmc_0_PIM1_InitDone_pin =3D> test_PIM1_InitDone_pin, > =A0 =A0 mpmc_0_PIM1_RdFIFO_Latency_pin =3D> test_PIM1_RdFIFO_Latency_pin, > =A0 =A0 mpmc_0_PIM1_RdFIFO_Flush_pin =3D> test_PIM1_RdFIFO_Flush_pin, > =A0 =A0 mpmc_0_PIM1_RdFIFO_Empty_pin =3D> test_PIM1_RdFIFO_Empty_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_Flush_pin =3D> test_PIM1_WrFIFO_Flush_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_AlmostFull_pin =3D> > test_PIM1_WrFIFO_AlmostFull_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_Empty_pin =3D> test_PIM1_WrFIFO_Empty_pin, > =A0 =A0 mpmc_0_PIM1_RdFIFO_RdWdAddr_pin =3D> test_PIM1_RdFIFO_RdWdAddr_pi=
n,
> =A0 =A0 mpmc_0_PIM1_RdFIFO_Pop_pin =3D> test_PIM1_RdFIFO_Pop_pin, > =A0 =A0 mpmc_0_PIM1_RdFIFO_Data_pin =3D> test_PIM1_RdFIFO_Data_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_Push_pin =3D> test_PIM1_WrFIFO_Push_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_BE_pin =3D> test_PIM1_WrFIFO_BE_pin, > =A0 =A0 mpmc_0_PIM1_WrFIFO_Data_pin =3D> test_PIM1_WrFIFO_Data_pin, > =A0 =A0 mpmc_0_PIM1_RdModWr_pin =3D> test_PIM1_RdModWr_pin, > =A0 =A0 mpmc_0_PIM1_Size_pin =3D> test_PIM1_Size_pin, > =A0 =A0 mpmc_0_PIM1_RNW_pin =3D> test_PIM1_RNW_pin, > =A0 =A0 mpmc_0_PIM1_AddrAck_pin =3D> test_PIM1_AddrAck_pin, > =A0 =A0 mpmc_0_PIM1_AddrReq_pin =3D> test_PIM1_AddrReq_pin, > =A0 =A0 mpmc_0_PIM1_Addr_pin =3D> test_PIM1_Addr_pin > =A0 ); > > ddr1:mt47h64m16 PORT map( > =A0 =A0 =A0 =A0 ODT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_ODT_pin(0),
> =A0 =A0 =A0 =A0 CK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Clk_pin(0),
> =A0 =A0 =A0 =A0 CKNeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_Clk_n_pin(0), > =A0 =A0 =A0 =A0 CKE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_CE_pin(0),
> =A0 =A0 =A0 =A0 CSNeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_CS_n_pin(0), > =A0 =A0 =A0 =A0 RASNeg =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_RAS_n_pin, > =A0 =A0 =A0 =A0 CASNeg =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_CAS_n_pin, > =A0 =A0 =A0 =A0 WENeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_WE_n_pin, > =A0 =A0 =A0 =A0 LDM =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DM_pin(0),
> =A0 =A0 =A0 =A0 UDM =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DM_pin(1),
> =A0 =A0 =A0 =A0 BA0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(0),
> =A0 =A0 =A0 =A0 BA1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(1),
> =A0 =A0 =A0 =A0 BA2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(2),
> =A0 =A0 =A0 =A0 A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(0),
> =A0 =A0 =A0 =A0 A1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(1),
> =A0 =A0 =A0 =A0 A2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(2),
> =A0 =A0 =A0 =A0 A3 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(3),
> =A0 =A0 =A0 =A0 A4 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(4),
> =A0 =A0 =A0 =A0 A5 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(5),
> =A0 =A0 =A0 =A0 A6 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(6),
> =A0 =A0 =A0 =A0 A7 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(7),
> =A0 =A0 =A0 =A0 A8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(8),
> =A0 =A0 =A0 =A0 A9 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(9),
> =A0 =A0 =A0 =A0 A10 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(10),
> =A0 =A0 =A0 =A0 A11 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(11),
> =A0 =A0 =A0 =A0 A12 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(12),
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DQ0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =3D> test_DDR2_DQ(0),
> =A0 =A0 =A0 =A0 DQ1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(1),
> =A0 =A0 =A0 =A0 DQ2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(2),
> =A0 =A0 =A0 =A0 DQ3 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(3),
> =A0 =A0 =A0 =A0 DQ4 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(4),
> =A0 =A0 =A0 =A0 DQ5 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(5),
> =A0 =A0 =A0 =A0 DQ6 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(6),
> =A0 =A0 =A0 =A0 DQ7 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(7),
> =A0 =A0 =A0 =A0 DQ8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(8),
> =A0 =A0 =A0 =A0 DQ9 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(9),
> =A0 =A0 =A0 =A0 DQ10 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(10), > =A0 =A0 =A0 =A0 DQ11 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(11), > =A0 =A0 =A0 =A0 DQ12 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(12), > =A0 =A0 =A0 =A0 DQ13 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(13), > =A0 =A0 =A0 =A0 DQ14 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(14), > =A0 =A0 =A0 =A0 DQ15 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(15), > =A0 =A0 =A0 =A0 UDQS =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQS(0), > =A0 =A0 =A0 =A0 UDQSNeg =A0 =A0 =A0 =A0 =3D> test_DDR2_DQS_n(0), > =A0 =A0 =A0 =A0 LDQS =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQS(1), > =A0 =A0 =A0 =A0 LDQSNeg =A0 =A0 =A0 =A0 =3D> test_DDR2_DQS_n(1) > =A0 =A0 ); > > ddr2:mt47h64m16 PORT map( > =A0 =A0 =A0 =A0 ODT =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_ODT_pin(0),
> =A0 =A0 =A0 =A0 CK =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Clk_pin(0),
> =A0 =A0 =A0 =A0 CKNeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_Clk_n_pin(0), > =A0 =A0 =A0 =A0 CKE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_CE_pin(0),
> =A0 =A0 =A0 =A0 CSNeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_CS_n_pin(0), > =A0 =A0 =A0 =A0 RASNeg =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_RAS_n_pin, > =A0 =A0 =A0 =A0 CASNeg =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_CAS_n_pin, > =A0 =A0 =A0 =A0 WENeg =A0 =A0 =A0 =A0 =A0 =3D> test_DDR2_WE_n_pin, > =A0 =A0 =A0 =A0 LDM =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DM_pin(2),
> =A0 =A0 =A0 =A0 UDM =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DM_pin(3),
> =A0 =A0 =A0 =A0 BA0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(0),
> =A0 =A0 =A0 =A0 BA1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(1),
> =A0 =A0 =A0 =A0 BA2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_BankAddr_pin(2),
> =A0 =A0 =A0 =A0 A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(0),
> =A0 =A0 =A0 =A0 A1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(1),
> =A0 =A0 =A0 =A0 A2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(2),
> =A0 =A0 =A0 =A0 A3 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(3),
> =A0 =A0 =A0 =A0 A4 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(4),
> =A0 =A0 =A0 =A0 A5 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(5),
> =A0 =A0 =A0 =A0 A6 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(6),
> =A0 =A0 =A0 =A0 A7 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(7),
> =A0 =A0 =A0 =A0 A8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(8),
> =A0 =A0 =A0 =A0 A9 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_D=
DR2_Addr_pin(9),
> =A0 =A0 =A0 =A0 A10 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(10),
> =A0 =A0 =A0 =A0 A11 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(11),
> =A0 =A0 =A0 =A0 A12 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_Addr_pin(12),
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DQ0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =3D> test_DDR2_DQ(16),
> =A0 =A0 =A0 =A0 DQ1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(17),
> =A0 =A0 =A0 =A0 DQ2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(18),
> =A0 =A0 =A0 =A0 DQ3 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(19),
> =A0 =A0 =A0 =A0 DQ4 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(20),
> =A0 =A0 =A0 =A0 DQ5 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(21),
> =A0 =A0 =A0 =A0 DQ6 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(22),
> =A0 =A0 =A0 =A0 DQ7 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(23),
> =A0 =A0 =A0 =A0 DQ8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(24),
> =A0 =A0 =A0 =A0 DQ9 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> test_DDR=
2_DQ(25),
> =A0 =A0 =A0 =A0 DQ10 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(26), > =A0 =A0 =A0 =A0 DQ11 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(27), > =A0 =A0 =A0 =A0 DQ12 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(28), > =A0 =A0 =A0 =A0 DQ13 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(29), > =A0 =A0 =A0 =A0 DQ14 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(30), > =A0 =A0 =A0 =A0 DQ15 =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQ(21), > =A0 =A0 =A0 =A0 UDQS =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQS(2), > =A0 =A0 =A0 =A0 UDQSNeg =A0 =A0 =A0 =A0 =3D> test_DDR2_DQS_n(2), > =A0 =A0 =A0 =A0 LDQS =A0 =A0 =A0 =A0 =A0 =A0=3D> test_DDR2_DQS(3), > =A0 =A0 =A0 =A0 LDQSNeg =A0 =A0 =A0 =A0 =3D> test_DDR2_DQS_n(3) > =A0 =A0 ); > > =A0 sys_clk_pin <=3D not sys_clk_pin after 5 ns; > =A0 sys_rst_pin <=3D '1' after 50 ns; > > end architecture test; > > ####################################################################
Reply by simax October 29, 20082008-10-29
Hello



Im trying to simulate the MPMC with an DDR2 Memory. Ive got the
problem that the mpmc wont initialise the ddr2 modul. The
Idelayctrl_Rdy_I is 1 but it wont talk to the memory. Im using the
mt47h64m16 memory modul from freemodelfoundry.

My mpmc is instantiated  with :

BEGIN mpmc
 PARAMETER INSTANCE = mpmc_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_MEM_PARTNO = MT47H64M16-3
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_PIM1_BASETYPE = 4
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_MPMC_BASEADDR = 0xA0000000
 PARAMETER C_MPMC_HIGHADDR = 0xAFFFFFFF
 PARAMETER C_MEM_DATA_WIDTH = 32
 BUS_INTERFACE SPLB0 = mb_plb
 PORT MPMC_Clk90 = clk_125_90
 PORT MPMC_Clk_200MHz = clk_200_0
 PORT MPMC_Clk0 = sys_clk_s
 PORT MPMC_Rst = sys_rst_s
 PORT DDR2_DQS_n = mpmc_0_DDR2_DQS_n
 PORT DDR2_DQS = mpmc_0_DDR2_DQS
 PORT DDR2_DM = mpmc_0_DDR2_DM
 PORT DDR2_DQ = mpmc_0_DDR2_DQ
 PORT DDR2_Addr = mpmc_0_DDR2_Addr
 PORT DDR2_BankAddr = mpmc_0_DDR2_BankAddr
 PORT DDR2_WE_n = mpmc_0_DDR2_WE_n
 PORT DDR2_CAS_n = mpmc_0_DDR2_CAS_n
 PORT DDR2_RAS_n = mpmc_0_DDR2_RAS_n
 PORT DDR2_ODT = mpmc_0_DDR2_ODT
 PORT DDR2_CS_n = mpmc_0_DDR2_CS_n
 PORT DDR2_CE = mpmc_0_DDR2_CE
 PORT DDR2_Clk_n = mpmc_0_DDR2_Clk_n
 PORT DDR2_Clk = mpmc_0_DDR2_Clk
 PORT PIM1_InitDone = mpmc_0_PIM1_InitDone
 PORT PIM1_RdFIFO_Latency = mpmc_0_PIM1_RdFIFO_Latency
 PORT PIM1_RdFIFO_Flush = mpmc_0_PIM1_RdFIFO_Flush
 PORT PIM1_RdFIFO_Empty = mpmc_0_PIM1_RdFIFO_Empty
 PORT PIM1_WrFIFO_Flush = mpmc_0_PIM1_WrFIFO_Flush
 PORT PIM1_WrFIFO_AlmostFull = mpmc_0_PIM1_WrFIFO_AlmostFull
 PORT PIM1_WrFIFO_Empty = mpmc_0_PIM1_WrFIFO_Empty
 PORT PIM1_RdFIFO_RdWdAddr = mpmc_0_PIM1_RdFIFO_RdWdAddr
 PORT PIM1_RdFIFO_Pop = mpmc_0_PIM1_RdFIFO_Pop
 PORT PIM1_RdFIFO_Data = mpmc_0_PIM1_RdFIFO_Data
 PORT PIM1_WrFIFO_Push = mpmc_0_PIM1_WrFIFO_Push
 PORT PIM1_WrFIFO_BE = mpmc_0_PIM1_WrFIFO_BE
 PORT PIM1_WrFIFO_Data = mpmc_0_PIM1_WrFIFO_Data
 PORT PIM1_RdModWr = mpmc_0_PIM1_RdModWr
 PORT PIM1_Size = mpmc_0_PIM1_Size
 PORT PIM1_RNW = mpmc_0_PIM1_RNW
 PORT PIM1_AddrAck = mpmc_0_PIM1_AddrAck
 PORT PIM1_AddrReq = mpmc_0_PIM1_AddrReq
 PORT PIM1_Addr = mpmc_0_PIM1_Addr
END



and i connected them in a test file (see bottom of this post...)

 Please help me and tell me what is missing or wrong...



thx



####################################################################

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
USE STD.textio.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;




LIBRARY FMF;       USE FMF.gen_utils.ALL;
                   USE FMF.conversions.ALL;

entity system_test is
end system_test;

architecture test of system_test is

component system is
  port (
    fpga_0_LEDS_GPIO_d_out_pin : out std_logic_vector(0 to 31);
    sys_clk_pin : in std_logic;
    sys_rst_pin : in std_logic;
    mpmc_0_DDR2_DQS_n : inout std_logic_vector(3 downto 0);
    mpmc_0_DDR2_DQS : inout std_logic_vector(3 downto 0);
    mpmc_0_DDR2_DM_pin : out std_logic_vector(3 downto 0);
    mpmc_0_DDR2_DQ : inout std_logic_vector(31 downto 0);
    mpmc_0_DDR2_Addr_pin : out std_logic_vector(12 downto 0);
    mpmc_0_DDR2_BankAddr_pin : out std_logic_vector(2 downto 0);
    mpmc_0_DDR2_WE_n_pin : out std_logic;
    mpmc_0_DDR2_CAS_n_pin : out std_logic;
    mpmc_0_DDR2_RAS_n_pin : out std_logic;
    mpmc_0_DDR2_ODT_pin : out std_logic_vector(0 to 0);
    mpmc_0_DDR2_CS_n_pin : out std_logic_vector(0 to 0);
    mpmc_0_DDR2_CE_pin : out std_logic_vector(0 to 0);
    mpmc_0_DDR2_Clk_n_pin : out std_logic_vector(0 to 0);
    mpmc_0_DDR2_Clk_pin : out std_logic_vector(0 to 0);
    mpmc_0_PIM1_InitDone_pin : out std_logic;
    mpmc_0_PIM1_RdFIFO_Latency_pin : out std_logic_vector(1 downto 0);
    mpmc_0_PIM1_RdFIFO_Flush_pin : in std_logic;
    mpmc_0_PIM1_RdFIFO_Empty_pin : out std_logic;
    mpmc_0_PIM1_WrFIFO_Flush_pin : in std_logic;
    mpmc_0_PIM1_WrFIFO_AlmostFull_pin : out std_logic;
    mpmc_0_PIM1_WrFIFO_Empty_pin : out std_logic;
    mpmc_0_PIM1_RdFIFO_RdWdAddr_pin : out std_logic_vector(3 downto
0);
    mpmc_0_PIM1_RdFIFO_Pop_pin : in std_logic;
    mpmc_0_PIM1_RdFIFO_Data_pin : out std_logic_vector(63 downto 0);
    mpmc_0_PIM1_WrFIFO_Push_pin : in std_logic;
    mpmc_0_PIM1_WrFIFO_BE_pin : in std_logic_vector(7 downto 0);
    mpmc_0_PIM1_WrFIFO_Data_pin : in std_logic_vector(63 downto 0);
    mpmc_0_PIM1_RdModWr_pin : in std_logic;
    mpmc_0_PIM1_Size_pin : in std_logic_vector(3 downto 0);
    mpmc_0_PIM1_RNW_pin : in std_logic;
    mpmc_0_PIM1_AddrAck_pin : out std_logic;
    mpmc_0_PIM1_AddrReq_pin : in std_logic;
    mpmc_0_PIM1_Addr_pin : in std_logic_vector(31 downto 0)
  );
end component;

component mt47h64m16 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_ODT          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CK           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKNeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDM          : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDM          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA0          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA2          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ0          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ8          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ9          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ10         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ11         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ12         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ13         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ14         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ15         : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDQS         : VitalDelayType01 := VitalZeroDelay01;
        tipd_UDQSNeg      : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDQS         : VitalDelayType01 := VitalZeroDelay01;
        tipd_LDQSNeg      : VitalDelayType01 := VitalZeroDelay01;

        -- tpd delays
        tpd_CK_DQ0        : VitalDelayType01Z := UnitDelay01Z; --
tAC(max), tHZ
        tpd_CK_DQ1        : VitalDelayType := UnitDelay; -- tAC(min)
        tpd_CK_LDQS       : VitalDelayType01Z := UnitDelay01Z; --
tDQSCK(max)

        -- tsetup values
        tsetup_DQ0_LDQS   : VitalDelayType := UnitDelay; -- tDSb
        tsetup_A0_CK      : VitalDelayType := UnitDelay; -- tISb
        tsetup_LDQS_CK_CL3_negedge_posedge: VitalDelayType :=
UnitDelay; -- tDSS
        tsetup_LDQS_CK_CL4_negedge_posedge: VitalDelayType :=
UnitDelay; -- tDSS
        tsetup_LDQS_CK_CL5_negedge_posedge: VitalDelayType :=
UnitDelay; -- tDSS
        tsetup_LDQS_CK_CL6_negedge_posedge: VitalDelayType :=
UnitDelay; -- tDSS

        -- thold values
        thold_DQ0_LDQS    : VitalDelayType := UnitDelay; -- tDHb
        thold_A0_CK       : VitalDelayType := UnitDelay; -- tIHb
        thold_LDQS_CK_CL3_posedge_posedge : VitalDelayType :=
UnitDelay; -- tDSH
        thold_LDQS_CK_CL4_posedge_posedge : VitalDelayType :=
UnitDelay; -- tDSH
        thold_LDQS_CK_CL5_posedge_posedge : VitalDelayType :=
UnitDelay; -- tDSH
        thold_LDQS_CK_CL6_posedge_posedge : VitalDelayType :=
UnitDelay; -- tDSH

        -- tpw values
        tpw_CK_CL3_posedge: VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL3_negedge: VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL4_posedge: VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL4_negedge: VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL5_posedge: VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL5_negedge: VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL6_posedge: VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL6_negedge: VitalDelayType := UnitDelay; -- tCLAVG
        tpw_A0_CL3        : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL4        : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL5        : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL6        : VitalDelayType := UnitDelay; -- tIPW
        tpw_DQ0_CL3       : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL4       : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL5       : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL6       : VitalDelayType := UnitDelay; -- tDIPW
        tpw_LDQS_normCL3_posedge : VitalDelayType := UnitDelay; --
tDQSH
        tpw_LDQS_normCL3_negedge : VitalDelayType := UnitDelay; --
tDQSL
        tpw_LDQS_normCL4_posedge : VitalDelayType := UnitDelay; --
tDQSH
        tpw_LDQS_normCL4_negedge : VitalDelayType := UnitDelay; --
tDQSL
        tpw_LDQS_normCL5_posedge : VitalDelayType := UnitDelay; --
tDQSH
        tpw_LDQS_normCL5_negedge : VitalDelayType := UnitDelay; --
tDQSL
        tpw_LDQS_normCL6_posedge : VitalDelayType := UnitDelay; --
tDQSH
        tpw_LDQS_normCL6_negedge : VitalDelayType := UnitDelay; --
tDQSL
        tpw_LDQS_preCL3_negedge  : VitalDelayType := UnitDelay; --
tWPRE
        tpw_LDQS_preCL4_negedge  : VitalDelayType := UnitDelay; --
tWPRE
        tpw_LDQS_preCL5_negedge  : VitalDelayType := UnitDelay; --
tWPRE
        tpw_LDQS_preCL6_negedge  : VitalDelayType := UnitDelay; --
tWPRE
        tpw_LDQS_postCL3_negedge : VitalDelayType := UnitDelay; --
tWPST
        tpw_LDQS_postCL4_negedge : VitalDelayType := UnitDelay; --
tWPST
        tpw_LDQS_postCL5_negedge : VitalDelayType := UnitDelay; --
tWPST
        tpw_LDQS_postCL6_negedge : VitalDelayType := UnitDelay; --
tWPST

        -- tperiod values
        tperiod_CK_CL3    : VitalDelayType := UnitDelay; --
tCKAVG(min)
        tperiod_CK_CL4    : VitalDelayType := UnitDelay; --
tCKAVG(min)
        tperiod_CK_CL5    : VitalDelayType := UnitDelay; --
tCKAVG(min)
        tperiod_CK_CL6    : VitalDelayType := UnitDelay; --
tCKAVG(min)

        -- tskew values
        tskew_CK_LDQS_CL3_posedge_posedge: VitalDelayType :=
UnitDelay; -- tDQSS
        tskew_CK_LDQS_CL4_posedge_posedge: VitalDelayType :=
UnitDelay; -- tDQSS
        tskew_CK_LDQS_CL5_posedge_posedge: VitalDelayType :=
UnitDelay; -- tDQSS
        tskew_CK_LDQS_CL6_posedge_posedge: VitalDelayType :=
UnitDelay; -- tDQSS

        -- tdevice values: values for internal delays
        tdevice_tRC       : VitalDelayType    := 54 ns; -- tRC
        tdevice_tRRD      : VitalDelayType    := 10 ns; -- tRRD
        tdevice_tRCD      : VitalDelayType    := 12 ns; -- tRCD
        tdevice_tFAW      : VitalDelayType    := 50 ns; -- tFAW
        tdevice_tRASMIN   : VitalDelayType    := 40 ns; -- tRAS(min)
        tdevice_tRASMAX   : VitalDelayType    := 70 us; -- tRAS(max)
        tdevice_tRTP      : VitalDelayType    := 7.5 ns; -- tRTP
        tdevice_tWR       : VitalDelayType    := 15 ns; -- tWR
        tdevice_tWTR      : VitalDelayType    := 7.5 ns; -- tWTR
        tdevice_tRP       : VitalDelayType    := 12 ns; -- tRP
        tdevice_tRFCMIN   : VitalDelayType    := 127.5 ns; --
tRFC(min)
        tdevice_tRFCMAX   : VitalDelayType    := 70 us; -- tRFC(max)
        tdevice_REFPer    : VitalDelayType    := 64 ms; -- refresh
period
        tdevice_tCKAVGMAX : VitalDelayType    := 8 ns; -- tCKAVG(max)

        -- generic control parameters
        InstancePath      : string    := DefaultInstancePath;
        TimingChecksOn    : boolean   := DefaultTimingChecks;
        MsgOn             : boolean   := DefaultMsgOn;
        XOn               : boolean   := DefaultXon;

        -- memory file to be loaded
        mem_file_name     : string    := "none";
        UserPreload       : boolean   := FALSE;

        -- For FMF SDF technology file usage
        TimingModel       : string    := DefaultTimingModel
    );
    PORT (
        ODT             : IN    std_ulogic := 'U';
        CK              : IN    std_ulogic := 'U';
        CKNeg           : IN    std_ulogic := 'U';
        CKE             : IN    std_ulogic := 'U';
        CSNeg           : IN    std_ulogic := 'U';
        RASNeg          : IN    std_ulogic := 'U';
        CASNeg          : IN    std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        LDM             : IN    std_ulogic := 'U';
        UDM             : IN    std_ulogic := 'U';
        BA0             : IN    std_ulogic := 'U';
        BA1             : IN    std_ulogic := 'U';
        BA2             : IN    std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        DQ0             : INOUT std_ulogic := 'U';
        DQ1             : INOUT std_ulogic := 'U';
        DQ2             : INOUT std_ulogic := 'U';
        DQ3             : INOUT std_ulogic := 'U';
        DQ4             : INOUT std_ulogic := 'U';
        DQ5             : INOUT std_ulogic := 'U';
        DQ6             : INOUT std_ulogic := 'U';
        DQ7             : INOUT std_ulogic := 'U';
        DQ8             : INOUT std_ulogic := 'U';
        DQ9             : INOUT std_ulogic := 'U';
        DQ10            : INOUT std_ulogic := 'U';
        DQ11            : INOUT std_ulogic := 'U';
        DQ12            : INOUT std_ulogic := 'U';
        DQ13            : INOUT std_ulogic := 'U';
        DQ14            : INOUT std_ulogic := 'U';
        DQ15            : INOUT std_ulogic := 'U';
        UDQS            : INOUT std_ulogic := 'U';
        UDQSNeg         : INOUT std_ulogic := 'U';
        LDQS            : INOUT std_ulogic := 'U';
        LDQSNeg         : INOUT std_ulogic := 'U'
    );

END component;


signal fpga_0_LEDS_GPIO_d_out_pin : std_logic_vector(0 to 31);
signal sys_clk_pin :  std_logic :='0';
signal sys_rst_pin :  std_logic :='0';
signal test_DDR2_DQS_n :  std_logic_vector(3 downto 0);
signal test_DDR2_DQS :  std_logic_vector(3 downto 0);
signal test_DDR2_DM_pin :  std_logic_vector(3 downto 0);
signal test_DDR2_DQ :  std_logic_vector(31 downto 0);
signal test_DDR2_Addr_pin :  std_logic_vector(12 downto 0);
signal test_DDR2_BankAddr_pin :  std_logic_vector(2 downto 0);
signal test_DDR2_WE_n_pin :  std_logic;
signal test_DDR2_CAS_n_pin :  std_logic;
signal test_DDR2_RAS_n_pin :  std_logic;
signal test_DDR2_ODT_pin :  std_logic_vector(0 to 0);
signal test_DDR2_CS_n_pin :  std_logic_vector(0 to 0);
signal test_DDR2_CE_pin :  std_logic_vector(0 to 0);
signal test_DDR2_Clk_n_pin :  std_logic_vector(0 to 0);
signal test_DDR2_Clk_pin :  std_logic_vector(0 to 0);
signal test_PIM1_InitDone_pin :  std_logic;
signal test_PIM1_RdFIFO_Latency_pin :  std_logic_vector(1 downto 0);
signal test_PIM1_RdFIFO_Flush_pin :  std_logic:='0';
signal test_PIM1_RdFIFO_Empty_pin :  std_logic;
signal test_PIM1_WrFIFO_Flush_pin :  std_logic:='0';
signal test_PIM1_WrFIFO_AlmostFull_pin :  std_logic;
signal test_PIM1_WrFIFO_Empty_pin :  std_logic;
signal test_PIM1_RdFIFO_RdWdAddr_pin :  std_logic_vector(3 downto
0):=(others =>'0');
signal test_PIM1_RdFIFO_Pop_pin :  std_logic:='0';
signal test_PIM1_RdFIFO_Data_pin :  std_logic_vector(63 downto
0):=(others =>'0');
signal test_PIM1_WrFIFO_Push_pin :  std_logic:='0';
signal test_PIM1_WrFIFO_BE_pin :  std_logic_vector(7 downto
0):=(others =>'0');
signal test_PIM1_WrFIFO_Data_pin :  std_logic_vector(63 downto
0):=(others =>'0');
signal test_PIM1_RdModWr_pin :  std_logic:='0';
signal test_PIM1_Size_pin :  std_logic_vector(3 downto 0):=(others
=>'0');
signal test_PIM1_RNW_pin :  std_logic:='0';
signal test_PIM1_AddrAck_pin :  std_logic :='0';
signal test_PIM1_AddrReq_pin :  std_logic:='0';
signal test_PIM1_Addr_pin :  std_logic_vector(31 downto 0):=(others
=>'0');


begin

dut: system
  port map (
    fpga_0_LEDS_GPIO_d_out_pin =>fpga_0_LEDS_GPIO_d_out_pin,
    sys_clk_pin => sys_clk_pin,
    sys_rst_pin => sys_rst_pin,
    mpmc_0_DDR2_DQS_n => test_DDR2_DQS_n,
    mpmc_0_DDR2_DQS => test_DDR2_DQS,
    mpmc_0_DDR2_DM_pin => test_DDR2_DM_pin,
    mpmc_0_DDR2_DQ => test_DDR2_DQ,
    mpmc_0_DDR2_Addr_pin => test_DDR2_Addr_pin,
    mpmc_0_DDR2_BankAddr_pin => test_DDR2_BankAddr_pin,
    mpmc_0_DDR2_WE_n_pin => test_DDR2_WE_n_pin,
    mpmc_0_DDR2_CAS_n_pin => test_DDR2_CAS_n_pin,
    mpmc_0_DDR2_RAS_n_pin => test_DDR2_RAS_n_pin,
    mpmc_0_DDR2_ODT_pin => test_DDR2_ODT_pin,
    mpmc_0_DDR2_CS_n_pin => test_DDR2_CS_n_pin,
    mpmc_0_DDR2_CE_pin => test_DDR2_CE_pin,
    mpmc_0_DDR2_Clk_n_pin => test_DDR2_Clk_n_pin,
    mpmc_0_DDR2_Clk_pin => test_DDR2_Clk_pin,
    mpmc_0_PIM1_InitDone_pin => test_PIM1_InitDone_pin,
    mpmc_0_PIM1_RdFIFO_Latency_pin => test_PIM1_RdFIFO_Latency_pin,
    mpmc_0_PIM1_RdFIFO_Flush_pin => test_PIM1_RdFIFO_Flush_pin,
    mpmc_0_PIM1_RdFIFO_Empty_pin => test_PIM1_RdFIFO_Empty_pin,
    mpmc_0_PIM1_WrFIFO_Flush_pin => test_PIM1_WrFIFO_Flush_pin,
    mpmc_0_PIM1_WrFIFO_AlmostFull_pin =>
test_PIM1_WrFIFO_AlmostFull_pin,
    mpmc_0_PIM1_WrFIFO_Empty_pin => test_PIM1_WrFIFO_Empty_pin,
    mpmc_0_PIM1_RdFIFO_RdWdAddr_pin => test_PIM1_RdFIFO_RdWdAddr_pin,
    mpmc_0_PIM1_RdFIFO_Pop_pin => test_PIM1_RdFIFO_Pop_pin,
    mpmc_0_PIM1_RdFIFO_Data_pin => test_PIM1_RdFIFO_Data_pin,
    mpmc_0_PIM1_WrFIFO_Push_pin => test_PIM1_WrFIFO_Push_pin,
    mpmc_0_PIM1_WrFIFO_BE_pin => test_PIM1_WrFIFO_BE_pin,
    mpmc_0_PIM1_WrFIFO_Data_pin => test_PIM1_WrFIFO_Data_pin,
    mpmc_0_PIM1_RdModWr_pin => test_PIM1_RdModWr_pin,
    mpmc_0_PIM1_Size_pin => test_PIM1_Size_pin,
    mpmc_0_PIM1_RNW_pin => test_PIM1_RNW_pin,
    mpmc_0_PIM1_AddrAck_pin => test_PIM1_AddrAck_pin,
    mpmc_0_PIM1_AddrReq_pin => test_PIM1_AddrReq_pin,
    mpmc_0_PIM1_Addr_pin => test_PIM1_Addr_pin
  );

ddr1:mt47h64m16 PORT map(
        ODT			=> test_DDR2_ODT_pin(0),
        CK			=> test_DDR2_Clk_pin(0),
        CKNeg		=> test_DDR2_Clk_n_pin(0),
        CKE			=> test_DDR2_CE_pin(0),
        CSNeg		=> test_DDR2_CS_n_pin(0),
        RASNeg		=> test_DDR2_RAS_n_pin,
        CASNeg		=> test_DDR2_CAS_n_pin,
        WENeg		=> test_DDR2_WE_n_pin,
        LDM			=> test_DDR2_DM_pin(0),
        UDM			=> test_DDR2_DM_pin(1),
        BA0			=> test_DDR2_BankAddr_pin(0),
        BA1			=> test_DDR2_BankAddr_pin(1),
        BA2			=> test_DDR2_BankAddr_pin(2),
        A0			=> test_DDR2_Addr_pin(0),
        A1			=> test_DDR2_Addr_pin(1),
        A2			=> test_DDR2_Addr_pin(2),
        A3			=> test_DDR2_Addr_pin(3),
        A4			=> test_DDR2_Addr_pin(4),
        A5			=> test_DDR2_Addr_pin(5),
        A6			=> test_DDR2_Addr_pin(6),
        A7			=> test_DDR2_Addr_pin(7),
        A8			=> test_DDR2_Addr_pin(8),
        A9			=> test_DDR2_Addr_pin(9),
        A10			=> test_DDR2_Addr_pin(10),
        A11			=> test_DDR2_Addr_pin(11),
        A12			=> test_DDR2_Addr_pin(12),
		DQ0			=> test_DDR2_DQ(0),
        DQ1			=> test_DDR2_DQ(1),
        DQ2			=> test_DDR2_DQ(2),
        DQ3			=> test_DDR2_DQ(3),
        DQ4			=> test_DDR2_DQ(4),
        DQ5			=> test_DDR2_DQ(5),
        DQ6			=> test_DDR2_DQ(6),
        DQ7			=> test_DDR2_DQ(7),
        DQ8			=> test_DDR2_DQ(8),
        DQ9			=> test_DDR2_DQ(9),
        DQ10		=> test_DDR2_DQ(10),
        DQ11		=> test_DDR2_DQ(11),
        DQ12		=> test_DDR2_DQ(12),
        DQ13		=> test_DDR2_DQ(13),
        DQ14		=> test_DDR2_DQ(14),
        DQ15		=> test_DDR2_DQ(15),
        UDQS		=> test_DDR2_DQS(0),
        UDQSNeg		=> test_DDR2_DQS_n(0),
        LDQS		=> test_DDR2_DQS(1),
        LDQSNeg		=> test_DDR2_DQS_n(1)
    );


ddr2:mt47h64m16 PORT map(
        ODT			=> test_DDR2_ODT_pin(0),
        CK			=> test_DDR2_Clk_pin(0),
        CKNeg		=> test_DDR2_Clk_n_pin(0),
        CKE			=> test_DDR2_CE_pin(0),
        CSNeg		=> test_DDR2_CS_n_pin(0),
        RASNeg		=> test_DDR2_RAS_n_pin,
        CASNeg		=> test_DDR2_CAS_n_pin,
        WENeg		=> test_DDR2_WE_n_pin,
        LDM			=> test_DDR2_DM_pin(2),
        UDM			=> test_DDR2_DM_pin(3),
        BA0			=> test_DDR2_BankAddr_pin(0),
        BA1			=> test_DDR2_BankAddr_pin(1),
        BA2			=> test_DDR2_BankAddr_pin(2),
        A0			=> test_DDR2_Addr_pin(0),
        A1			=> test_DDR2_Addr_pin(1),
        A2			=> test_DDR2_Addr_pin(2),
        A3			=> test_DDR2_Addr_pin(3),
        A4			=> test_DDR2_Addr_pin(4),
        A5			=> test_DDR2_Addr_pin(5),
        A6			=> test_DDR2_Addr_pin(6),
        A7			=> test_DDR2_Addr_pin(7),
        A8			=> test_DDR2_Addr_pin(8),
        A9			=> test_DDR2_Addr_pin(9),
        A10			=> test_DDR2_Addr_pin(10),
        A11			=> test_DDR2_Addr_pin(11),
        A12			=> test_DDR2_Addr_pin(12),
		DQ0			=> test_DDR2_DQ(16),
        DQ1			=> test_DDR2_DQ(17),
        DQ2			=> test_DDR2_DQ(18),
        DQ3			=> test_DDR2_DQ(19),
        DQ4			=> test_DDR2_DQ(20),
        DQ5			=> test_DDR2_DQ(21),
        DQ6			=> test_DDR2_DQ(22),
        DQ7			=> test_DDR2_DQ(23),
        DQ8			=> test_DDR2_DQ(24),
        DQ9			=> test_DDR2_DQ(25),
        DQ10		=> test_DDR2_DQ(26),
        DQ11		=> test_DDR2_DQ(27),
        DQ12		=> test_DDR2_DQ(28),
        DQ13		=> test_DDR2_DQ(29),
        DQ14		=> test_DDR2_DQ(30),
        DQ15		=> test_DDR2_DQ(21),
        UDQS		=> test_DDR2_DQS(2),
        UDQSNeg		=> test_DDR2_DQS_n(2),
        LDQS		=> test_DDR2_DQS(3),
        LDQSNeg		=> test_DDR2_DQS_n(3)
    );





  sys_clk_pin <= not sys_clk_pin after 5 ns;
  sys_rst_pin <= '1' after 50 ns;


end architecture test;

####################################################################