On Feb 3, 8:12=A0am, jhal...@TheWorld.com (Joseph H Allen) wrote:
> I'm surprised that the Spartan-6 integrated memory controller does not su=
pport
> DIMMs. =A0Also surprised that there are no integrated memory controllers =
in
> Virtex-6.

If the memory controller is a hard version of what's in the EDK, you
won't want to use it ...

-a

-jg wrote:
>> It more a question of die space. 3.3v tolerant IO is huge in 40/45nm.
>> In V6 they are trying to reach the high end of IO and LUT counts. On
>> the other hand with S6 the LUT counts are not that high and also the IO
>> count is lower than in V6 so they can waste space for the IO.
> 
> Die Size, are you sure ?
> - My understanding is Oxide thickness is what primarily determines IO
> Voltage Specs.
> 
> Die area (PAD IO area) more determines drive current.

Oxide thickness is one parameter in the equation. As you mentioned drive
current affects also heavily the pad area, and for 3.3v that is a
problematic area. I should have said just 3.3v IO not 3.3v tolerant IO.
3.3v can be done in 40nm process without major tweaking, but you pay in
the IO size.

For example in CycloneIII (65nm part) the maximum drive current for 3.3v
LVCMOS IO is 2mA which is very small making the IO standard almost
unusable (8mA with LVTTL which is not so great either).

--Kim

In article <9l9jo4dh2jaf45ko2vvadc51bn4chdcnt4@4ax.com>,
Brian Drummond  <brian@shapes.demon.co.uk> wrote:
>On Tue, 3 Feb 2009 15:12:41 +0000 (UTC), jhallen@TheWorld.com (Joseph H Allen)
>wrote:
>
>>I'm surprised that the Spartan-6 integrated memory controller does not support
>>DIMMs.  Also surprised that there are no integrated memory controllers in
>>Virtex-6.

>Reading between the lines here...

>At a guess the V6 I/O blocks are fast enough to support DDR memory quite well
>without special support - and that way you have the flexibility to support any
>configuration you need (modulo SSO limitations; the tools will handle those)

I'm thinking an integrated memory controller would be valuable in Virtex-6
because then designers would not have to go through the effort of using MIG. 
It works, but is still a lot of effort to make a high performance memory
interface.  Also why waste LUTs on a memory interface?  I want the LUTs for
my design, not for glue logic to make their chip work with SDRAM.  Finally,
DDR3 support is not really integrated in MIG.

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

On Tue, 3 Feb 2009 18:14:23 +0100, "Jan Bruns" <testzugang_janbruns@arcor.de>
wrote:

>
>"Joseph H Allen":
>> Benjamin Couillard  <benjamin.couillard@gmail.com> wrote:
>>>On 3 f&#4294967295;v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
>>>> I'm surprised that the Spartan-6 integrated memory controller does not support
>>>> DIMMs. Also surprised that there are no integrated memory controllers in
>>>> Virtex-6.
>>>>
>>>> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! 2.5V is the
>>>> new 5V...
>>>
>>>3.3V is the new 5V you might say
>
>> No, 3.3V was the old new 5V.  The new new 5V is 2.5V.  Altera Straitx-IV
>> also does not support 3.3V I/O.
>
>Hm, ok, the old 5V-TTL logic devices pobably weren't compatible with
>tube-level logic.

Heh - maybe they were.

If you wanted a high current PSU in those days, it tended to be 6.3V AC.
Now if you multiply by sqrt(2), subtract a couple of diode drops, 10% for
regulation, 5% for line tolerance, a volt for ripple, and enough for a linear
regulator... you're about 5V.

- Brian

On Tue, 3 Feb 2009 15:12:41 +0000 (UTC), jhallen@TheWorld.com (Joseph H Allen)
wrote:

>I'm surprised that the Spartan-6 integrated memory controller does not support
>DIMMs.  Also surprised that there are no integrated memory controllers in
>Virtex-6.
>
>Note the Virtex-6 Select-IO voltage range: only up to 2.5V!  2.5V is the
>new 5V...

Reading between the lines here...

At a guess the V6 I/O blocks are fast enough to support DDR memory quite well
without special support - and that way you have the flexibility to support any
configuration you need (modulo SSO limitations; the tools will handle those)

But the S6 would struggle without special support... which would explain why it
has blocks the V6 doesn't. It is targetted at lower cost apps where you rarely
need DIMMs. But at a guess you may be able to support DIMMs with some speed
limitations; maybe you can tap into the memory controllers for all except the
datapath.

- Brian

On Feb 4, 11:15=A0pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
> -jg wrote:
> > That's =A0a large market to isolate your devices from - one hopes the
> > few picoseconds of speed that might have gained, turn out to be wrth
> > it!! :)
>
> It more a question of die space. 3.3v tolerant IO is huge in 40/45nm.
> In V6 they are trying to reach the high end of IO and LUT counts. On
> the other hand with S6 the LUT counts are not that high and also the IO
> count is lower than in V6 so they can waste space for the IO.

Die Size, are you sure ?
- My understanding is Oxide thickness is what primarily determines IO
Voltage Specs.

Die area (PAD IO area) more determines drive current.

-jg

-jg wrote:
> So it seems they made a deliberate process decision, for Virtex 6 to
> be
> 2.5V, and Spartan 6 to be 3.3V ?

One decision maker might be, that usually new expensive designs are
not interfacing very old chips. But on the other hand cheap chips
can be used to cost reduce old designs or replace old ASICs.


> That's  a large market to isolate your devices from - one hopes the
> few picoseconds of speed that might have gained, turn out to be wrth
> it!! :)

It more a question of die space. 3.3v tolerant IO is huge in 40/45nm.
In V6 they are trying to reach the high end of IO and LUT counts. On
the other hand with S6 the LUT counts are not that high and also the IO
count is lower than in V6 so they can waste space for the IO.

--Kim

On Feb 4, 5:58=A0pm, Eric Smith <e...@brouhaha.com> wrote:
> -jg <Jim.Granvi...@gmail.com> writes:
> > The Spartan 6 Guide says Standards up to 3.3V ?
> > Where is the 2.5V limit given ?
>
> In the Virtex 6 guide.

So it seems they made a deliberate process decision, for Virtex 6 to
be
2.5V, and Spartan 6 to be 3.3V ?

That's  a large market to isolate your devices from - one hopes the
few picoseconds of speed that might have gained, turn out to be wrth
it!! :)

-jg
.

Jan Bruns <testzugang_janbruns@arcor.de> wrote:
 
> "glen herrmannsfeldt":
>> Jan Bruns <testzugang_janbruns@arcor.de> wrote:
>>> Will that Spartan6 have internal tristatable interconnects,
 
>> As far as I know, that will never happen again.  It is part
>> of the scaling laws for MOS circuits that as the circuitry
>> gets smaller the RC time constant of wires increases.  
>> R increases faster than C decreases, resulting in slower
>> circuits.  The fix is to add buffers on longer lines,
>> but those are directional.
 
> That's probably not 100% fpga related, but why would R and C
> change with smaller devices? Shouldn't R be constant for wires
> (halfed length and width), and C shrink with either the
> wire's surface or at most be constant shorter distance to 
> other lines, but shorter)? 

Wires shrink in width and height, both of which change
the resistance, C depends (mostly) just on width. 
Shrink by a factor of 2, R increases by a factor
of (about) 4, C decreases by a factor of 2.

If you actually shrink the die then the length would
also decrease, but it is more usual to keep the die size
and put more CLBs on.
 
> BTW.: I mean a way to get wired a AND/OR, using some 
> driver enable (to avoid MUXing many lines).
 
>>> and/or better capabilites to build large MUXes?
 
>> This should be possible.  As far as I know, AND/OR logic,
(snip)
 
> Sure, but there are only two options for an input to a mux:
> register or combinatorial. If it is combinatorial, there might 
> be a chance to absorb the AND with enable. If it's a register,
> we have a "wasted" LUT per MUX-input.
> The large OR at the end also adds levels of logic.

When you did have tristate devices on the chip interior
they were in special places, complicating routing.
 
>>> In Spartan3, a usual way to make a 32:1 MUX requires 16 LUT4
>>> (8 Slices, 2 CLBs) + F5MUX + 3 levels of FXMUXes and because
>>> both CLBs won't absorb much of any logic following the mux32,
>>> the result has to be routed far away.
 
>> Can you replace that with AND/OR logic?  
 
> That could probably mean 
> 32 LUT4s for (en & src & a0 & a1)
> 11 LUT4s to OR the 32 signals
> 8 LUT4s for a a2..a4 3->8 decoder 
> ========
> 61 LUT4s (much more then the 16 LUTs using a standard spartan3 MUX32)

Plus the priority encoder to use for the MUX inputs?

As I understand it, some tools will convert a wide (bus)
MUX into a decode and AND/OR logic.  For a single MUX
that doesn't seem to help.

-- glen

Joseph H Allen wrote:
> No, 3.3V was the old new 5V.  The new new 5V is 2.5V.  Altera Straitx-IV
> also does not support 3.3V I/O.

Also in some of the new chips that still support the 3.3v volt the drive
strength might be very low, even so low that is is almost unusable.

--Kim