"Bruno Cardeira" <bmscc@netcabo.pt> wrote in message news:<407086f8$0$3532$a729d347@news.telepac.pt>...
> Hello,
> does anyone know if it is possible to connect several Xilinx XC9536 CPLD
> output pins in a Wired-OR configuration?
> If possible, how can I do it in VHDL?
>
> Thanks
> Best Regards
> Bruno
OK. Lots of responses already to your problem.
A small remark regarding the use of strong pullups or pulldown
resistors: they are of course required if you need speed and may not
integrate more complex logic, but are power hungry. Obvious !
However, I had a problem like that one day, and solved it differently.
If the output pins you want to wire-or may be driven by a sequential
state machine AND no contention can occur (by definition of the
problem for instance), it is not difficult to build a state machine
that drives the wire-or bus 1 or more clocks at the value required,
and finally ends up by driving the bus to its rest (idle) state for 1
more clock (even maybe half a clock).
Then, idle state is kept by weak pullups or pulldowns or keeper
circuits if any.
Reply by Peter Alfke●April 8, 20042004-04-08
I meant to write:
... or even 330 Ohm at 3.3 V...
Peter
===========
> From: Peter Alfke <peter@xilinx.com>
> Organization: Xilinx,Inc
> Newsgroups: comp.arch.fpga
> Date: Thu, 08 Apr 2004 08:34:20 -0700
> Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
>
> If you want reasonable speed, then use 470 Ohm (10 mA @ 5V) or even at 3.3
> V. Higher resistors give long risetime. If that is acceptable, you can use
> something like 5.6 k.
> Peter Alfke
>
>> From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
>> Newsgroups: comp.arch.fpga
>> Date: Thu, 8 Apr 2004 16:03:15 +0300
>> Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
>>
>> I think, yes. You'll pull the line up by resistor (several kilos?). CPLD
>> will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0
>> otherwise. The same can be applied to pull-down resistor and '1', 'Z'
>> drivers. Line will be zero when nothing drives it. If CPLD outputs support
>> 'Z' state then I see no problem.
>>
>>
>> "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message
>> news:40748144$0$15193$a729d347@news.telepac.pt...
>>> Thanks for the help valentin.
>>>
>>> I want to use the Xilinx XC9536.
>>> If I use a pull-down resitor, I can do a Wired-OR with several pins,
>> right?
>>>
>>> Bruno
>>>
>>>
>>> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na
>>> mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de...
>>>>
>>>> The one I can think of:
>>>>
>>>> if OR_REDUCE(drivers) = '1' then
>>>> w <= DRIVE(1)
>>>> else
>>>> w <= DRIVE(0);
>>>>
>>>>
>>>>
>>>>
>>>> Externally, you would pull-up a line by resistor to Vcc and implement
>>>> transistor internally in FPGA:
>>>>
>>>> O <= '0' when A = '0' else 'Z';
>>>>
>>>> cheers.
>>>>
>>>>
>>>
>>>
>>
>>
>
Reply by Peter Alfke●April 8, 20042004-04-08
If you want reasonable speed, then use 470 Ohm (10 mA @ 5V) or even at 3.3
V. Higher resistors give long risetime. If that is acceptable, you can use
something like 5.6 k.
Peter Alfke
> From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
> Newsgroups: comp.arch.fpga
> Date: Thu, 8 Apr 2004 16:03:15 +0300
> Subject: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
>
> I think, yes. You'll pull the line up by resistor (several kilos?). CPLD
> will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0
> otherwise. The same can be applied to pull-down resistor and '1', 'Z'
> drivers. Line will be zero when nothing drives it. If CPLD outputs support
> 'Z' state then I see no problem.
>
>
> "Bruno Cardeira" <bmscc@netcabo.pt> wrote in message
> news:40748144$0$15193$a729d347@news.telepac.pt...
>> Thanks for the help valentin.
>>
>> I want to use the Xilinx XC9536.
>> If I use a pull-down resitor, I can do a Wired-OR with several pins,
> right?
>>
>> Bruno
>>
>>
>> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na
>> mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de...
>>>
>>> The one I can think of:
>>>
>>> if OR_REDUCE(drivers) = '1' then
>>> w <= DRIVE(1)
>>> else
>>> w <= DRIVE(0);
>>>
>>>
>>>
>>>
>>> Externally, you would pull-up a line by resistor to Vcc and implement
>>> transistor internally in FPGA:
>>>
>>> O <= '0' when A = '0' else 'Z';
>>>
>>> cheers.
>>>
>>>
>>
>>
>
>
Reply by valentin tihomirov●April 8, 20042004-04-08
I think, yes. You'll pull the line up by resistor (several kilos?). CPLD
will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0
otherwise. The same can be applied to pull-down resistor and '1', 'Z'
drivers. Line will be zero when nothing drives it. If CPLD outputs support
'Z' state then I see no problem.
"Bruno Cardeira" <bmscc@netcabo.pt> wrote in message
news:40748144$0$15193$a729d347@news.telepac.pt...
> Thanks for the help valentin.
>
> I want to use the Xilinx XC9536.
> If I use a pull-down resitor, I can do a Wired-OR with several pins,
right?
>
> Bruno
>
>
> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na
> mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de...
> >
> > The one I can think of:
> >
> > if OR_REDUCE(drivers) = '1' then
> > w <= DRIVE(1)
> > else
> > w <= DRIVE(0);
> >
> >
> >
> >
> > Externally, you would pull-up a line by resistor to Vcc and implement
> > transistor internally in FPGA:
> >
> > O <= '0' when A = '0' else 'Z';
> >
> > cheers.
> >
> >
>
>
Reply by Bruno Cardeira●April 7, 20042004-04-07
Thanks for the help valentin.
I want to use the Xilinx XC9536.
If I use a pull-down resitor, I can do a Wired-OR with several pins, right?
Bruno
"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> escreveu na
mensagem news:c4q2p8$2krd9u$1@ID-212430.news.uni-berlin.de...
>
> The one I can think of:
>
> if OR_REDUCE(drivers) = '1' then
> w <= DRIVE(1)
> else
> w <= DRIVE(0);
>
>
>
>
> Externally, you would pull-up a line by resistor to Vcc and implement
> transistor internally in FPGA:
>
> O <= '0' when A = '0' else 'Z';
>
> cheers.
>
>
Reply by valentin tihomirov●April 4, 20042004-04-04
The one I can think of:
if OR_REDUCE(drivers) = '1' then
w <= DRIVE(1)
else
w <= DRIVE(0);
Externally, you would pull-up a line by resistor to Vcc and implement
transistor internally in FPGA:
O <= '0' when A = '0' else 'Z';
cheers.
Reply by Bruno Cardeira●April 4, 20042004-04-04
Hello,
does anyone know if it is possible to connect several Xilinx XC9536 CPLD
output pins in a Wired-OR configuration?
If possible, how can I do it in VHDL?
Thanks
Best Regards
Bruno