On 11 May 2004 18:43:17 -0700, rajarsheeb@yahoo.com (raj) wrote:
>Hi,
>
>I have my design files in Verilog,but want to have my
>testbenches in VHDL.I think this is possible.
>Can anybody suggest some pointers to this.
>I am using ModelSim 5.7g and Xilinx Project Navigator 6.2.
No problem, as long as you have the (expensive) Modelsim license that
allows co-simulation. Check your license.
Regards,
Allan.
Reply by raj●May 11, 20042004-05-11
Hi,
I have my design files in Verilog,but want to have my
testbenches in VHDL.I think this is possible.
Can anybody suggest some pointers to this.
I am using ModelSim 5.7g and Xilinx Project Navigator 6.2.
--raj