On 06/12/2010 14:54, rickman wrote:
> On Dec 6, 3:24 am, David Brown<da...@westcontrol.removethisbit.com>
> wrote:
>> On 03/12/2010 18:02, Rob Gaddi wrote:
>>
>>
>>
>>> On 12/3/2010 12:45 AM, David Brown wrote:
>>>> Hi,
>>
>>>> I haven't a lot of experience with FPGA design, but have done a few
>>>> projects - mostly with Altera Cyclones, some with a Nios II. We are
>>>> looking at making a new design that should be low cost, but needs a high
>>>> speed serial interface (for reading in a DVI and/or HDMI signal).
>>
>>>> The obvious choice then is Lattice ECP3 (but I am very happy to hear
>>>> alternative suggestions).
>>
>>>> I've already had a look at quite a bit of the website, so I'll looking
>>>> mainly for information that is not there - a website will seldom tell
>>>> you that their software feels slow and awkward, or fast and intuitive.
>>>> And a website will often tell you things are free or "low cost", but the
>>>> small print and hidden costs are, well, small and hidden.
>>
>>>> I haven't used any Lattice tools for nearly ten years, and that was for
>>>> CPLD design. My guess is that things have changed a little since then.
>>
>>>> Are there anything major problems or obstacles that should make me
>>>> reconsider before getting in too deep? I'd like to avoid doing the
>>>> design and then finding out that Lattice only sells in 10,000
>>>> quantities, or that the tools are useless without buying many
>>>> kilodollars of third-party software.
>>
>>>> For the development software, I can only name a few features of Quartus
>>>> and ask if Lattice software is similar. I like the integration of
>>>> Quartus - it feels like a single coordinated tool. Is that also the case
>>>> with modern Lattice software? The tools I used long ago felt more like a
>>>> collection of different bits and pieces, such as two separate synthesis
>>>> engines that couldn't agree on anything.
>>
>>>> I also like Quartus SOPC builder - we might be putting a micro and a
>>>> DDR2 memory interface in this design, and SOPC builder is definitely a
>>>> convenient way to set put this together. Does Lattice have something
>>>> similar? Obviously it will be geared towards the Micro32 rather than the
>>>> Nios, but that's fine by me.
>>
>>>> How are the free tools compared to the paid-for tools? I'm okay with
>>>> paying for the tools if that's necessary, but it is very nice having
>>>> free versions that will do a good job. Amongst other things, it makes it
>>>> more convenient to work from different computers (such as at a home
>>>> office).
>>
>>>> Finally, there is the question of ready-made IP. The main parts I'd be
>>>> interested in here are a DDR2 memory interface, an embedded micro, and
>>>> possibly a DVI/HDMI receiver. I gather the micro32 is ready to use, free
>>>> (and open), and has a full gcc toolchain, so that should be a simple
>>>> choice (and the micro8 is a smaller alternative). It may be that I'll
>>>> have to make all or part of the DVI/HDMI receiver, though it would be
>>>> nice to get ready-made if it's not /too/ expensive. But the DDR2
>>>> interface is definitely something we should get ready-made.
>>
>>>> Thanks for any hints, pointers or opinions.
>>
>>>> mvh.,
>>
>>>> David
>>
>>> No experience with the Lattice parts, and only just switching to A from
>>> X recently. But, if you're currently happy with the Altera tools, I seem
>>> to recall the Arria II chips being price competitive with ECP3. Also,
>>> have you looked at the Cyclone IV GX chips? They've got high speed
>>> serial too, although I think availability may be an issue.
>>
>> The Arria II are probably price-competitive with the ECP3 when you get
>> above a certain size, but the ECP3 series starts lower.  We don't need a
>> great deal out of the FPGA other than the video interface, an embedded
>> micro (and even that is optional) and fast external memory.  The Cyclone
>> IV GX are a definite possibility - unfortunately the currently-available
>> EP4CGX15 is too small (though the price is nice), while the EP4CGX110 is
>> far too big.  The EP4CGX22 or 30 would be more appropriate, if they existed.
>>
>> I'm beginning to think that we'll drop the HDMI input.  It would be nice
>> to have an integrated solution, but it looks like it will be much more
>> cost-effective to have an external HDMI receiver chip and just read in
>> the data as a wide data bus.  Then we can use a Cyclone III or Cyclone
>> IV with the tools we have used before.
>
> That's an interesting trade off.  Lattice came out with SERDES on
> their low cost chips as a marketing move because neither X or A
> offered SERDES on their low cost lines.  Your preference may be to
> stick with the higher cost approach of using an additional chip rather
> than going with a new company and new tools. I can't say I blame you
> really.  I don't have that concern with any of X, A or L.  I guess
> I've used all three enough to be confident that I can make my design
> work regardless.
>

I am now looking at a C3 or C4 with an external HDMI receiver, because 
it I think it would be cheaper than an ECP3 with an integrated HDMI/DVI 
receiver.  An integrated solution would be more elegant, but the price 
difference between an ECP3 (with enough other resources) and a roughly 
equivalent C3 or C4 is greater than the cost of an HDMI receiver chip. 
The ECP3 may be "low cost" for an FPGA with high speed serial links, but 
that's only relative to a other FPGAs with high speed links.  And then 
there's the development costs and possible IP licensing costs to 
consider - reading a 36-bit parallel RGB bus is easy compared to 
implementing a HDMI/DVI receiver block.

In the end, however, it's up to the customer.  I'm not sure an FPGA 
solution is going to be possible within the hoped-for budget.  We are 
also looking at various system-on-a-chip devices to see if any of them 
can meet the requirements.

Thanks for your information and advice,

David

On Dec 6, 3:24=A0am, David Brown <da...@westcontrol.removethisbit.com>
wrote:
> On 03/12/2010 18:02, Rob Gaddi wrote:
>
>
>
> > On 12/3/2010 12:45 AM, David Brown wrote:
> >> Hi,
>
> >> I haven't a lot of experience with FPGA design, but have done a few
> >> projects - mostly with Altera Cyclones, some with a Nios II. We are
> >> looking at making a new design that should be low cost, but needs a hi=
gh
> >> speed serial interface (for reading in a DVI and/or HDMI signal).
>
> >> The obvious choice then is Lattice ECP3 (but I am very happy to hear
> >> alternative suggestions).
>
> >> I've already had a look at quite a bit of the website, so I'll looking
> >> mainly for information that is not there - a website will seldom tell
> >> you that their software feels slow and awkward, or fast and intuitive.
> >> And a website will often tell you things are free or "low cost", but t=
he
> >> small print and hidden costs are, well, small and hidden.
>
> >> I haven't used any Lattice tools for nearly ten years, and that was fo=
r
> >> CPLD design. My guess is that things have changed a little since then.
>
> >> Are there anything major problems or obstacles that should make me
> >> reconsider before getting in too deep? I'd like to avoid doing the
> >> design and then finding out that Lattice only sells in 10,000
> >> quantities, or that the tools are useless without buying many
> >> kilodollars of third-party software.
>
> >> For the development software, I can only name a few features of Quartu=
s
> >> and ask if Lattice software is similar. I like the integration of
> >> Quartus - it feels like a single coordinated tool. Is that also the ca=
se
> >> with modern Lattice software? The tools I used long ago felt more like=
 a
> >> collection of different bits and pieces, such as two separate synthesi=
s
> >> engines that couldn't agree on anything.
>
> >> I also like Quartus SOPC builder - we might be putting a micro and a
> >> DDR2 memory interface in this design, and SOPC builder is definitely a
> >> convenient way to set put this together. Does Lattice have something
> >> similar? Obviously it will be geared towards the Micro32 rather than t=
he
> >> Nios, but that's fine by me.
>
> >> How are the free tools compared to the paid-for tools? I'm okay with
> >> paying for the tools if that's necessary, but it is very nice having
> >> free versions that will do a good job. Amongst other things, it makes =
it
> >> more convenient to work from different computers (such as at a home
> >> office).
>
> >> Finally, there is the question of ready-made IP. The main parts I'd be
> >> interested in here are a DDR2 memory interface, an embedded micro, and
> >> possibly a DVI/HDMI receiver. I gather the micro32 is ready to use, fr=
ee
> >> (and open), and has a full gcc toolchain, so that should be a simple
> >> choice (and the micro8 is a smaller alternative). It may be that I'll
> >> have to make all or part of the DVI/HDMI receiver, though it would be
> >> nice to get ready-made if it's not /too/ expensive. But the DDR2
> >> interface is definitely something we should get ready-made.
>
> >> Thanks for any hints, pointers or opinions.
>
> >> mvh.,
>
> >> David
>
> > No experience with the Lattice parts, and only just switching to A from
> > X recently. But, if you're currently happy with the Altera tools, I see=
m
> > to recall the Arria II chips being price competitive with ECP3. Also,
> > have you looked at the Cyclone IV GX chips? They've got high speed
> > serial too, although I think availability may be an issue.
>
> The Arria II are probably price-competitive with the ECP3 when you get
> above a certain size, but the ECP3 series starts lower. =A0We don't need =
a
> great deal out of the FPGA other than the video interface, an embedded
> micro (and even that is optional) and fast external memory. =A0The Cyclon=
e
> IV GX are a definite possibility - unfortunately the currently-available
> EP4CGX15 is too small (though the price is nice), while the EP4CGX110 is
> far too big. =A0The EP4CGX22 or 30 would be more appropriate, if they exi=
sted.
>
> I'm beginning to think that we'll drop the HDMI input. =A0It would be nic=
e
> to have an integrated solution, but it looks like it will be much more
> cost-effective to have an external HDMI receiver chip and just read in
> the data as a wide data bus. =A0Then we can use a Cyclone III or Cyclone
> IV with the tools we have used before.

That's an interesting trade off.  Lattice came out with SERDES on
their low cost chips as a marketing move because neither X or A
offered SERDES on their low cost lines.  Your preference may be to
stick with the higher cost approach of using an additional chip rather
than going with a new company and new tools. I can't say I blame you
really.  I don't have that concern with any of X, A or L.  I guess
I've used all three enough to be confident that I can make my design
work regardless.

Rick

On Dec 6, 2:59=A0am, David Brown <da...@westcontrol.removethisbit.com>
wrote:
> On 03/12/2010 17:23, Gabor wrote:
>
> > I don't know if someone already covered this point, but the free
> > tools do not cover the ECP3 devices. =A0You'll need to buy the full
>
> I don't think anyone else pointed it out, but I've just noticed it
> myself. =A0It's not particularly expensive, but it's always an
> inconvenience when you have software locked to a particular machine. =A0I=
t
> makes it harder to split work between an office PC and a home PC.

I can't say about other tool vendors, but Lattice has always been very
good about licensing multiple machines.  When I originally bought the
tools they allowed me to license the two machine I used.  Then when I
replaced one they licensed the new machine as well.

> > license. Also as Raymund pointed out, the DDR memory controller is
> > additional money.
>
> Do you have any ideas about the price? =A0I have in the past heard prices
> for memory controllers and other common-place IPs that were a digit or
> two more than I would expect. =A0On the other hand, competitors like
> Altera include DDR controllers in their full license tools.

It all depends on the model.  One advantage of the Lattice IP is the
open source license on the Lattice CPUs.  If you invest the time in
creating code for the Lattice CPU, you won't have to port that to a
new CPU if you want to target a different brand of FPGA or move to an
ASIC.

Rick

On 03/12/2010 18:02, Rob Gaddi wrote:
> On 12/3/2010 12:45 AM, David Brown wrote:
>> Hi,
>>
>> I haven't a lot of experience with FPGA design, but have done a few
>> projects - mostly with Altera Cyclones, some with a Nios II. We are
>> looking at making a new design that should be low cost, but needs a high
>> speed serial interface (for reading in a DVI and/or HDMI signal).
>>
>> The obvious choice then is Lattice ECP3 (but I am very happy to hear
>> alternative suggestions).
>>
>>
>> I've already had a look at quite a bit of the website, so I'll looking
>> mainly for information that is not there - a website will seldom tell
>> you that their software feels slow and awkward, or fast and intuitive.
>> And a website will often tell you things are free or "low cost", but the
>> small print and hidden costs are, well, small and hidden.
>>
>>
>> I haven't used any Lattice tools for nearly ten years, and that was for
>> CPLD design. My guess is that things have changed a little since then.
>>
>> Are there anything major problems or obstacles that should make me
>> reconsider before getting in too deep? I'd like to avoid doing the
>> design and then finding out that Lattice only sells in 10,000
>> quantities, or that the tools are useless without buying many
>> kilodollars of third-party software.
>>
>>
>> For the development software, I can only name a few features of Quartus
>> and ask if Lattice software is similar. I like the integration of
>> Quartus - it feels like a single coordinated tool. Is that also the case
>> with modern Lattice software? The tools I used long ago felt more like a
>> collection of different bits and pieces, such as two separate synthesis
>> engines that couldn't agree on anything.
>>
>> I also like Quartus SOPC builder - we might be putting a micro and a
>> DDR2 memory interface in this design, and SOPC builder is definitely a
>> convenient way to set put this together. Does Lattice have something
>> similar? Obviously it will be geared towards the Micro32 rather than the
>> Nios, but that's fine by me.
>>
>>
>> How are the free tools compared to the paid-for tools? I'm okay with
>> paying for the tools if that's necessary, but it is very nice having
>> free versions that will do a good job. Amongst other things, it makes it
>> more convenient to work from different computers (such as at a home
>> office).
>>
>>
>> Finally, there is the question of ready-made IP. The main parts I'd be
>> interested in here are a DDR2 memory interface, an embedded micro, and
>> possibly a DVI/HDMI receiver. I gather the micro32 is ready to use, free
>> (and open), and has a full gcc toolchain, so that should be a simple
>> choice (and the micro8 is a smaller alternative). It may be that I'll
>> have to make all or part of the DVI/HDMI receiver, though it would be
>> nice to get ready-made if it's not /too/ expensive. But the DDR2
>> interface is definitely something we should get ready-made.
>>
>>
>> Thanks for any hints, pointers or opinions.
>>
>> mvh.,
>>
>> David
>>
>
> No experience with the Lattice parts, and only just switching to A from
> X recently. But, if you're currently happy with the Altera tools, I seem
> to recall the Arria II chips being price competitive with ECP3. Also,
> have you looked at the Cyclone IV GX chips? They've got high speed
> serial too, although I think availability may be an issue.
>

The Arria II are probably price-competitive with the ECP3 when you get 
above a certain size, but the ECP3 series starts lower.  We don't need a 
great deal out of the FPGA other than the video interface, an embedded 
micro (and even that is optional) and fast external memory.  The Cyclone 
IV GX are a definite possibility - unfortunately the currently-available 
EP4CGX15 is too small (though the price is nice), while the EP4CGX110 is 
far too big.  The EP4CGX22 or 30 would be more appropriate, if they existed.

I'm beginning to think that we'll drop the HDMI input.  It would be nice 
to have an integrated solution, but it looks like it will be much more 
cost-effective to have an external HDMI receiver chip and just read in 
the data as a wide data bus.  Then we can use a Cyclone III or Cyclone 
IV with the tools we have used before.

Thanks,

David

On 03/12/2010 17:23, Gabor wrote:

> I don't know if someone already covered this point, but the free
> tools do not cover the ECP3 devices.  You'll need to buy the full

I don't think anyone else pointed it out, but I've just noticed it 
myself.  It's not particularly expensive, but it's always an 
inconvenience when you have software locked to a particular machine.  It 
makes it harder to split work between an office PC and a home PC.

> license. Also as Raymund pointed out, the DDR memory controller is
> additional money.

Do you have any ideas about the price?  I have in the past heard prices 
for memory controllers and other common-place IPs that were a digit or 
two more than I would expect.  On the other hand, competitors like 
Altera include DDR controllers in their full license tools.

> I've developed a few products with Lattice ECP
> and ECP2 parts.  It's worth taking a good look at the clock routing
> to make sure you don't get in trouble with high-speed I/O logic.
> Specifically there are only a couple of edge clock routes per side of
> the parts and the sources for each route are limited. So it becomes
> hard to make multiple unrelated high-speed interfaces on one side of

Thanks for that tip.

> the chip.  Also the fabric is composed of memory-capable and
> non-memory-capable cells.  But coming from Altera I suppose having
> any distributed memory capability is a plus.  Finally another
> cost-cutting makes the four sides of the device have different
> subsets of the total available I/O standards or features, so again
> read carefully.
>
> I have not used the high-speed SERDES parts from Lattice, so I can't
> comment on that.  If you're trying to do something standard with it
> like DVI/HDMI try to get a reference design to make sure it's
> possible.  Lattice FAE's have been pretty helpful for us.
>

I see they have a kit with an HDMI demonstration.  It's not exactly 
cheap - it's the kind you buy when you have already made the decision on 
the platform, rather than the kind you use to help make the decision. 
But the fact that the boards exist is a good indication of what's possible.

Thanks,

David

On 12/3/2010 12:45 AM, David Brown wrote:
> Hi,
>
> I haven't a lot of experience with FPGA design, but have done a few
> projects - mostly with Altera Cyclones, some with a Nios II. We are
> looking at making a new design that should be low cost, but needs a high
> speed serial interface (for reading in a DVI and/or HDMI signal).
>
> The obvious choice then is Lattice ECP3 (but I am very happy to hear
> alternative suggestions).
>
>
> I've already had a look at quite a bit of the website, so I'll looking
> mainly for information that is not there - a website will seldom tell
> you that their software feels slow and awkward, or fast and intuitive.
> And a website will often tell you things are free or "low cost", but the
> small print and hidden costs are, well, small and hidden.
>
>
> I haven't used any Lattice tools for nearly ten years, and that was for
> CPLD design. My guess is that things have changed a little since then.
>
> Are there anything major problems or obstacles that should make me
> reconsider before getting in too deep? I'd like to avoid doing the
> design and then finding out that Lattice only sells in 10,000
> quantities, or that the tools are useless without buying many
> kilodollars of third-party software.
>
>
> For the development software, I can only name a few features of Quartus
> and ask if Lattice software is similar. I like the integration of
> Quartus - it feels like a single coordinated tool. Is that also the case
> with modern Lattice software? The tools I used long ago felt more like a
> collection of different bits and pieces, such as two separate synthesis
> engines that couldn't agree on anything.
>
> I also like Quartus SOPC builder - we might be putting a micro and a
> DDR2 memory interface in this design, and SOPC builder is definitely a
> convenient way to set put this together. Does Lattice have something
> similar? Obviously it will be geared towards the Micro32 rather than the
> Nios, but that's fine by me.
>
>
> How are the free tools compared to the paid-for tools? I'm okay with
> paying for the tools if that's necessary, but it is very nice having
> free versions that will do a good job. Amongst other things, it makes it
> more convenient to work from different computers (such as at a home
> office).
>
>
> Finally, there is the question of ready-made IP. The main parts I'd be
> interested in here are a DDR2 memory interface, an embedded micro, and
> possibly a DVI/HDMI receiver. I gather the micro32 is ready to use, free
> (and open), and has a full gcc toolchain, so that should be a simple
> choice (and the micro8 is a smaller alternative). It may be that I'll
> have to make all or part of the DVI/HDMI receiver, though it would be
> nice to get ready-made if it's not /too/ expensive. But the DDR2
> interface is definitely something we should get ready-made.
>
>
> Thanks for any hints, pointers or opinions.
>
> mvh.,
>
> David
>

No experience with the Lattice parts, and only just switching to A from 
X recently.  But, if you're currently happy with the Altera tools, I 
seem to recall the Arria II chips being price competitive with ECP3. 
Also, have you looked at the Cyclone IV GX chips?  They've got high 
speed serial too, although I think availability may be an issue.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Dec 3, 9:55=A0am, David Brown <da...@westcontrol.removethisbit.com>
wrote:
> On 03/12/2010 15:29, krakatoa wrote:
>
>
>
> >> On 03/12/2010 11:45, Michael Kellett wrote:
> >>> "David Brown"<da...@westcontrol.removethisbit.com> =A0 wrote in messa=
ge
> >>>news:uMOdncQg25wsMGXRnZ2dnUVZ8r6dnZ2d@lyse.net...
> >>>> Hi,
>
> >>>> I haven't a lot of experience with FPGA design, but have done a few
> >>>> projects - mostly with Altera Cyclones, some with a Nios II. =A0We a=
re
> >>>> looking at making a new design that should be low cost, but needs a
> > high
> >>>> speed serial interface (for reading in a DVI and/or HDMI signal).
>
> >>>> The obvious choice then is Lattice ECP3 (but I am very happy to hear
> >>>> alternative suggestions).
>
> >>>> I've already had a look at quite a bit of the website, so I'll looki=
ng
> >>>> mainly for information that is not there - a website will seldom tel=
l
> > you
> >>>> that their software feels slow and awkward, or fast and intuitive. A=
nd
> > a
> >>>> website will often tell you things are free or "low cost", but the
> > small
> >>>> print and hidden costs are, well, small and hidden.
>
> >>>> I haven't used any Lattice tools for nearly ten years, and that was
> > for
> >>>> CPLD design. =A0My guess is that things have changed a little since
> > then.
>
> >>>> Are there anything major problems or obstacles that should make me
> >>>> reconsider before getting in too deep? =A0I'd like to avoid doing th=
e
> > design
> >>>> and then finding out that Lattice only sells in 10,000 quantities, o=
r
> > that
> >>>> the tools are useless without buying many kilodollars of third-party
> >>>> software.
>
> >>>> For the development software, I can only name a few features of
> > Quartus
> >>>> and ask if Lattice software is similar. =A0I like the integration of
> >>>> Quartus - it feels like a single coordinated tool. =A0Is that also t=
he
> > case
> >>>> with modern Lattice software? =A0The tools I used long ago felt more=
 like
> > a
> >>>> collection of different bits and pieces, such as two separate
> > synthesis
> >>>> engines that couldn't agree on anything.
>
> >>>> I also like Quartus SOPC builder - we might be putting a micro and a
> > DDR2
> >>>> memory interface in this design, and SOPC builder is definitely a
> >>>> convenient way to set put this together. =A0Does Lattice have someth=
ing
> >>>> similar? =A0Obviously it will be geared towards the Micro32 rather t=
han
> > the
> >>>> Nios, but that's fine by me.
>
> >>>> How are the free tools compared to the paid-for tools? =A0I'm okay w=
ith
> >>>> paying for the tools if that's necessary, but it is very nice having
> > free
> >>>> versions that will do a good job. =A0Amongst other things, it makes =
it
> > more
> >>>> convenient to work from different computers (such as at a home
> > office).
>
> >>>> Finally, there is the question of ready-made IP. =A0The main parts I=
'd
> > be
> >>>> interested in here are a DDR2 memory interface, an embedded micro, a=
nd
> >>>> possibly a DVI/HDMI receiver. =A0I gather the micro32 is ready to us=
e,
> > free
> >>>> (and open), and has a full gcc toolchain, so that should be a simple
> >>>> choice (and the micro8 is a smaller alternative). =A0It may be that =
I'll
> >>>> have to make all or part of the DVI/HDMI receiver, though it would b=
e
> > nice
> >>>> to get ready-made if it's not /too/ expensive. =A0But the DDR2 inter=
face
> > is
> >>>> definitely something we should get ready-made.
>
> >>>> Thanks for any hints, pointers or opinions.
>
> >>>> mvh.,
>
> >>>> David
>
> > Hello,
>
> > As far as my short experience with ECP3 is concerned, I noted the
> > following:
>
> > - their PLL is much less configurable than the ones from Altera. You fi=
nd
> > yourself very often with unsynthesisable frequencies, and I remember it
> > being unable to make an output frequency less than 2 MHz whatever the i=
nput
> > frequency.
>
> I hope the figure of 2 MHz was a typo. =A0But that's useful information -
> I will need to be careful of which frequencies I need.
>
> > - their Reveal software (equivalent Signal Tap or Chipscope) is very sl=
ow
> > as soon as you put too many signals or too much memory. Let's say that =
you
> > put 15 signals with 1024k, you'll have to wait 15 or 20 seconds for you=
r
> > trigger to work and display the result.
>
> OK.
>
> > - The tools have a Xilinx "feel". I found it difficult sometimes to tra=
ce
> > the origin of a warning because not enough information is given. The Ch=
ip
> > and constraints Editor is not very easy to lauch (because if I am corre=
ct,
> > it is not really integrated to ISPLever) and to use. But maybe all thes=
e
> > cosmetic troubles will disappear with Diamond.
>
> OK - it looks like "Diamond" improves on this, but I haven't tried it yet=
.
>
> > Apart from that, the general feeling is good. I had no problem using so=
me
> > of their IP, no known bug or extra difficulties due to the technology. =
The
> > tools may look less professionnal than Altera or Xilinx, but in the end=
,
> > they have no bugs and it does not cost you a lot more in time to do the
> > job. And the FPGA works perfectly.
>
> Nice to know.
>
> Thanks,
>
> David

I don't know if someone already covered this point, but the free tools
do
not cover the ECP3 devices.  You'll need to buy the full license.
Also
as Raymund pointed out, the DDR memory controller is additional
money.  I've developed a few products with Lattice ECP and
ECP2 parts.  It's worth taking a good look at the clock routing
to make sure you don't get in trouble with high-speed I/O logic.
Specifically there are only a couple of edge clock routes per
side of the parts and the sources for each route are limited.
So it becomes hard to make multiple unrelated high-speed
interfaces on one side of the chip.  Also the fabric is composed
of memory-capable and non-memory-capable cells.  But
coming from Altera I suppose having any distributed memory
capability is a plus.  Finally another cost-cutting makes the
four sides of the device have different subsets of the total
available I/O standards or features, so again read carefully.

I have not used the high-speed SERDES parts from Lattice,
so I can't comment on that.  If you're trying to do something
standard with it like DVI/HDMI try to get a reference design
to make sure it's possible.  Lattice FAE's have been pretty
helpful for us.

Regards,
Gabor