If it's simply 2 halves of a design with a pipe between them I would
use LVDS as the pipe because it can be very predictable latency and
you can build that into the combined design as simply something that
looks like a normal register pipeline. As soon as you stick something
in that adds channel handling messaging, or retransmission of packets,
etc. maintaining that fixed latency is much more difficult.

If your board design isn't fixed you could add one or two more pairs
of LVDS to allow parity, frame sync, or even clock forwarding
techniques. The clock forwarding is a good technique because it is
simple but also the clock delay at the second chip then tends to track
the data variation with temperature, voltage, silicon batch etc.. This
avoids all the complication of recovery or syncing of data and you are
unlike to need any error detection as once it is setup correctly in
the design/board the link probably never fail.

John Adair
Enterpoint Ltd. - Home of Raggedstone3. The Cyclone-IV GX Development
Board.

On Jun 15, 3:59=C2=A0pm, Vivek Menon <vivek.meno...@gmail.com> wrote:
> I have a design partitioned over 2 FPGAs. I am trying to determine the be=
nefits of selecting GTX links vs. LVDS to transfer the data between FPGAs.
>
> Target Device =C2=A0: xc6vlx550t
> Target Package : ff1759
> Target Speed =C2=A0 : -2=EF=BB=BF
>
> Latency calculations:
> 1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20=
 bits input. This means the bits are transmitted at bit-rate =3D 20*106.25 =
MHz =3D 2.125 Gbps.
> # of bits to be transferred =3D 1728
> Latency of this interface =3D 1/(80% of bit-rate * (20/16)*(# of bits=EF=
=BB=BF transferred/16)) =3D 1/(2.295+e11) =3D 4.35+e-12 seconds
>
> 2. LVDS+Aurora: The Aurora interface is configured at 600MHz (6 Gbps) wit=
h lane width as 2 bytes.
>
> Latency of this interface =3D 1/(80% of clock rate * (# of bits=EF=BB=BF =
transferred/16)=EF=BB=BF) =3D 1/(5.184+e10) =3D 19.29+e-12 seconds
>
> Is this calculation correct? My assumption for the LVDS calculation is th=
at Aurora does not up-sample the clock frequency by 20 for transmitting dat=
a.
>
> Thanks in advance for all the feedback.

Vivek,

I've recently determined the latency of Aurora in my design by running
simulation. It's V6, 250Mhz, 20bit, no framing.
I've got 340ns. If there is a clock compensation, it periodically
inserts a symbol and adds an additional clock .

Thanks,
Evgeni

========================
http://outputlogic.com

>I have a design partitioned over 2 FPGAs. I am trying to determine the
bene=
>fits of selecting GTX links vs. LVDS to transfer the data between FPGAs.
>=20
>Target Device  : xc6vlx550t
>Target Package : ff1759
>Target Speed   : -2=EF=BB=BF
>=20
>Latency calculations:
>1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20
b=
>its input. This means the bits are transmitted at bit-rate =3D 20*106.25
MH=
>z =3D 2.125 Gbps.
># of bits to be transferred =3D 1728
>Latency of this interface =3D 1/(80% of bit-rate * (20/16)*(# of
bits=EF=BB=
>=BF transferred/16)) =3D 1/(2.295+e11) =3D 4.35+e-12 seconds
>=20
>2. LVDS+Aurora: The Aurora interface is configured at 600MHz (6 Gbps) with
=
>lane width as 2 bytes.
>=20
>Latency of this interface =3D 1/(80% of clock rate * (# of bits=EF=BB=BF
tr=
>ansferred/16)=EF=BB=BF) =3D 1/(5.184+e10) =3D 19.29+e-12 seconds
>=20
>=20
>Is this calculation correct? My assumption for the LVDS calculation is
that=
> Aurora does not up-sample the clock frequency by 20 for transmitting
data.
>=20
>Thanks in advance for all the feedback.
>
Generate both lots of IP.
Write a testbench with both instantiated.
Simulate.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

I have a design partitioned over 2 FPGAs. I am trying to determine the bene=
fits of selecting GTX links vs. LVDS to transfer the data between FPGAs.
=20
Target Device  : xc6vlx550t
Target Package : ff1759
Target Speed   : -2=EF=BB=BF
=20
Latency calculations:
1. GTX interface: The GTX transceiver is configured at 106.25 MHz with 20 b=
its input. This means the bits are transmitted at bit-rate =3D 20*106.25 MH=
z =3D 2.125 Gbps.
# of bits to be transferred =3D 1728
Latency of this interface =3D 1/(80% of bit-rate * (20/16)*(# of bits=EF=BB=
=BF transferred/16)) =3D 1/(2.295+e11) =3D 4.35+e-12 seconds
=20
2. LVDS+Aurora: The Aurora interface is configured at 600MHz (6 Gbps) with =
lane width as 2 bytes.
=20
Latency of this interface =3D 1/(80% of clock rate * (# of bits=EF=BB=BF tr=
ansferred/16)=EF=BB=BF) =3D 1/(5.184+e10) =3D 19.29+e-12 seconds
=20
=20
Is this calculation correct? My assumption for the LVDS calculation is that=
 Aurora does not up-sample the clock frequency by 20 for transmitting data.
=20
Thanks in advance for all the feedback.