Memory Reduced and Fast DDS Using FPGA
Direct digital synthesis is a method of creating arbitrary waveforms of desired frequency. A general DDS system comprises analog and digital part. Phase accumulator and LUT make digital part and DAC makes analog part. This paper presents 12 bit memory reduced FPGA based architecture of DDS. Phase truncation and quadrature symmetry of sine wave are used to achieve higher ROM compression. Dither is also used to achieve error free output. This design has been implemented on SPARTAN-3E FPGA with maximum clock frequency of 50 MHz. We have used LTC2624 quad DAC with 12 bit resolution which introduces very less amount of harmonics hence LPF is not needed. This design uses only 128 memory locations. Hence it is suitable for applications where system speed, memory and size of the system are main concern. Its wide and flexible range of frequency make it useful in RF transmission, Biomedical function generators and Modulation.
Summary
This 2010 paper describes a 12-bit, memory-reduced DDS implemented on a Xilinx Spartan-3E FPGA using phase truncation, quadrature symmetry and dithering to compress the sine LUT to just 128 entries. Readers will learn practical architecture and implementation details for low-memory, high-speed DDS designs and how to interface the digital output to a 12-bit DAC for minimal harmonic content.
Key Takeaways
- Apply phase truncation and quadrature symmetry to drastically reduce ROM/LUT size (to 128 entries) for sinusoid generation.
- Use dithering to counteract truncation error and suppress spurious tones in DDS outputs.
- Map a 12-bit DDS on a Spartan-3E FPGA and meet 50 MHz timing while minimizing resource usage.
- Interface the FPGA DDS to a 12-bit DAC (LTC2624) to obtain low-harmonic analog outputs without heavy analog filtering.
Who Should Read This
FPGA and DSP engineers with intermediate HDL experience who need compact, real-time waveform generators for resource-constrained embedded or instrumentation systems.
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