Summer of gateware is coming (again)
HistoricalIntermediate
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python...
Summary
Christopher Felton previews MyHDL's participation in Google Summer of Code 2016, describing community goals, candidate projects, and the project's place within FPGA toolchains. The post explains what the summer's gateware work aims to achieve and how contributors and mentors can get involved.
Key Takeaways
- Understand MyHDL's role in Google Summer of Code 2016 and the community objectives driving the effort.
- Learn how MyHDL integrates with Verilog and VHDL flows and fits into existing FPGA toolchains.
- Identify concrete project ideas and the steps to contribute or mentor during the GSoC cycle.
- Evaluate the practical benefits and limitations of using a Python-based approach for gateware development.
Who Should Read This
Intermediate FPGA/HDL engineers, Python developers, and students interested in contributing to MyHDL or applying for GSoC who want practical information on projects, workflows, and getting involved.
HistoricalIntermediate
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