My VHDL <= monpjc; Journey
I always like to start my first blog on a website with a bit of a introduction as to who I am and what I’ll be writting about. I feel this gives you the reader a opportunity to see where I’m coming from and understand a little of my point of view. So when I was asked to come and start blogging on FPGARelated I wondered what I should say. So for my first blog its all about how me, aka monpjc, and how I got into VHDL.
It started a long time ago when I was working for a company who were developing high speed data communications for SCSI and gigabit Ethernet. One of the contractors was the VHDL guru and it was he that introduced it to me. I quickly became hooked and wanted to understand more. My first bit of VHDL code was for our product that used Altera Flex chips and it interfaced between the core and SDRAM across clock boundaries. Shortly after leaving that company and having done a few hobby VHDL projects on MAX7000 chips I got offered a role designng development kits at a mobile phone chip manufacture who were developing 3G at the time. Unfortunately the offer fell though and I never got a FPGA based job after that. So since then VHDL has always been a hobby and unfortunately due to costs of chips and development tools, one that was hard to keep up with.
However over the last few years there has been significantly better Development kits available and this is making the option of learning, using and developing FPGA application more and more easy. The choice of using VHDL over Verilog is purely historical as that's what I was first introduced to. However I would say that having looked at both languages I still like VHDL more. To me it much more low level hardcore logic get your hands dirty type stuff.
I was always a very strong Altera person and had learnt to use the interface and in a way got used to the pain and poor work flow. Others may disagree with me in the same way they will disagree with my choice of VHDL and even more so when I slip back into using STD_LOGIC_ARCH from time to time. However when I got given the Xess XuLA FPGA development kit to try out I had to load the Xilinx IDE. With the help of a well written guide from Xess I have to say I fell for ISE in a big way and would now totally use Xilinx ISE as a first choice.
The tools available mean you no longer have to spend hundreds or thousands on kits and now pay less than you would at a local takeout. The range of kits start with the very newly introduced Tautic CPLD board going up though kits like the Xess XuLA, terasic DE0-Nano and Papillio One. However if you do have a few extra penny's then kits like the terasic DE2 are a great way to get into FPGAs. There are much larger kits, but I expect people with the cash and experience to have these as your starting to look at serious level of understanding.
I also get asked where to learn about FPGAs and how for example to learn VHDL. When I feel that lots of people spend time talking about it, looking for a guide or some guiding light. The only way to learn about FPGAs is to do it. That's right, buy a kit, install the IDE and start writing. You will get lots of compile errors and feel frustrated but start simple and build up. Don’t try to design the space shuttle, just a blinkly LED, then move up one step at a time. But for people really wanting guides then look at ones by real engineers and I’m biased as a VHDL lover; Xess Guide to FPGAs What Now, Free range VHDL and if you want a book then pick up a copy of ‘The Dsigner’s Guide to VHDL’. But just do it!
As a embedded electronics engineer spending most of my time with embedded micros like PICs I like the more simplistic designs, the cleaver things you can do with very little and showing that you done need a 32bit RTOS to blink a LED. So I like showing people what you can do with CPLDs and FPGAs at a entry level and this is something I’ve already been blogging about, even started blogging about simple logic too. So for you guys we need to step it up a little and take FPGAs one step on. So starting next month I’ll be looking at one of the common designs that people want to do and put in a FPGA, that being a CPU. I’ll look at why we even want to consider a CPU on a PIC and then look for a FREE not licenced way of doing this even if I have to design it from scratch. So I hope you will join me next time to start this journey.
Next post by Paul J Clarke:
State Machine ‘v’ Micro in a FPGA
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