Accounting for delay from multiple sources in delta-sigma ADCs

Delta-sigma analog-to-digital converters (ADCs) are ideal for converting analog signals over a wide range of frequencies, from DC to several megahertz; they are the only low cost conversion method that provides both high dynamic range and flexibility in converting low bandwidth input signals. Delta-sigma converters have found homes in such applications as communications systems, consumer and professional audio, industrial weight scales, and precision measurement devices

But, because Delta-sigma ADCs introduce delays into the signal chain, they have traditionally been relegated to high-resolution, very-low frequency applications.

Basically, these converters consist of an oversampling modulator followed by a low-pass digital/ decimation filter that together produce a high-resolution data-stream output. It is the phase response of the digital filter that is responsible for most of the delay in delta-sigma data converters (though a front-end amplifier, or logic interface may also contribute). This characteristic has prevented the use of these converters in multiplexed systems - it takes many clock cycles for the digital filter to settle after switching from one channel to the next.

However, the actual delay is predictable and deterministic. This paper discusses these sources of delay in depth and how all of the delays can be calculated with reasonable accuracy, allowing system designers to account for them in time-sensitive applications.