tri-state in altera

hi,
i m still in planning phase of my design. i was just looking at xilinx
and altera devices. Xilinx provides tri-state buffers as well as
tri-state lines whereas altera doesn't and suggests to use muxs
insteed of tri-state buffers.
Now assume that i have a bus in my design where lots of drivers are
there n driving bus through tri-state buffers. I am just wondering
what will happen if i implement this design in altera. I'll have to
take all drivers at one place, put a mux and re-route them to all
sink. won't it affect timing considerably.
considering it xilinx becomes obvious choice because of tri-state
buffers n lines. Anyone has any other opinion or observation on the
topic??

digari wrote:
> 
> hi,
> i m still in planning phase of my design. i was just looking at xilinx
> and altera devices. Xilinx provides tri-state buffers as well as
> tri-state lines whereas altera doesn't and suggests to use muxs
> insteed of tri-state buffers.
> Now assume that i have a bus in my design where lots of drivers are
> there n driving bus through tri-state buffers. I am just wondering
> what will happen if i implement this design in altera. I'll have to
> take all drivers at one place, put a mux and re-route them to all
> sink. won't it affect timing considerably.
> considering it xilinx becomes obvious choice because of tri-state
> buffers n lines. Anyone has any other opinion or observation on the
> topic??

The older Xilinx chips have lots of tristate buffers.  But they have
been phasing them out for the last two generations and have completed
that task with the Spartan 3 chips.  The internal tristate buffer is
dead!  

BTW, if you think routing signals to a common mux is slow, you should
check the timing numbers on the tbufs driving long lines which then run
around the chip.  If you do a really good job of placement, you can
minimize the speed penalty.  But tristate buffers will *always* be slow
due to the nature of a passive pullup.  

Altera has a cascade backbone inside their LABs that will AND the
outputs of the LUTs at a very high speed.  This can implement a very
wide AND-OR gate for wide muxes at high speed.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Yup,

Tristate is actually slower.

The tristate buffers in Virtex and all subsequent families are in fact 
separate bidirectional logic structures that simulate the behavior of a 
tristate bus.

http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf

see page 11:  Spartan 3 is faster and less expensive without any 
tristate elements at all!

Austin

rickman wrote:
> digari wrote:
> 
>>hi,
>>i m still in planning phase of my design. i was just looking at xilinx
>>and altera devices. Xilinx provides tri-state buffers as well as
>>tri-state lines whereas altera doesn't and suggests to use muxs
>>insteed of tri-state buffers.
>>Now assume that i have a bus in my design where lots of drivers are
>>there n driving bus through tri-state buffers. I am just wondering
>>what will happen if i implement this design in altera. I'll have to
>>take all drivers at one place, put a mux and re-route them to all
>>sink. won't it affect timing considerably.
>>considering it xilinx becomes obvious choice because of tri-state
>>buffers n lines. Anyone has any other opinion or observation on the
>>topic??
> 
> 
> The older Xilinx chips have lots of tristate buffers.  But they have
> been phasing them out for the last two generations and have completed
> that task with the Spartan 3 chips.  The internal tristate buffer is
> dead!  
> 
> BTW, if you think routing signals to a common mux is slow, you should
> check the timing numbers on the tbufs driving long lines which then run
> around the chip.  If you do a really good job of placement, you can
> minimize the speed penalty.  But tristate buffers will *always* be slow
> due to the nature of a passive pullup.  
> 
> Altera has a cascade backbone inside their LABs that will AND the
> outputs of the LUTs at a very high speed.  This can implement a very
> wide AND-OR gate for wide muxes at high speed.  
> 

digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>...
> hi,
> i m still in planning phase of my design. i was just looking at xilinx
> and altera devices. Xilinx provides tri-state buffers as well as
> tri-state lines whereas altera doesn't and suggests to use muxs
> insteed of tri-state buffers.
> Now assume that i have a bus in my design where lots of drivers are
> there n driving bus through tri-state buffers. I am just wondering
> what will happen if i implement this design in altera. I'll have to
> take all drivers at one place, put a mux and re-route them to all
> sink. won't it affect timing considerably.
> considering it xilinx becomes obvious choice because of tri-state
> buffers n lines. Anyone has any other opinion or observation on the
> topic??

On-chip tri-state is pretty near dead.  As metal has gotten slower
relative to transistors, making a long wire with multiple tri-state
drivers on it has become very slow, since there's no easy way to
re-buffer the signal (the signal could be flowing in one of two
directions, since there are multiple drive points).

For that reason, all Altera devices have relied on multiplexers to
make on-chip buses, rather than on-chip tri-states.

This approach is clearly winning out.  Recently a company (I forget
the name) filed a patent for SoC designs on ASICs where they use
multiplexers rather than tri-state buses.  So ASICs are following in
FPGA footsteps here.  Xilinx has also gradually abandoned on-chip
tri-states (the 4K had real tri-states, Virtex-2 has a dedicated
distributed mux, and Spartan-3 gets rid of that and relies on the
regular logic).  Altera has always used the regular logic approach.

So don't worry about the lack of on-chip tri-states in Altera devices
-- muxes are the way to go.  Note that once you're using muxes to
implement your buses, it also opens up the possibility of using more
general switching fabrics (in the limit a crossbar) rather than one
centralized bus.

Vaughn
Altera

Vaughn,

Yes, we do agree.  Nice to let folks know that we agree on many things.

Austin

Vaughn Betz wrote:
> digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>...
> 
>>hi,
>>i m still in planning phase of my design. i was just looking at xilinx
>>and altera devices. Xilinx provides tri-state buffers as well as
>>tri-state lines whereas altera doesn't and suggests to use muxs
>>insteed of tri-state buffers.
>>Now assume that i have a bus in my design where lots of drivers are
>>there n driving bus through tri-state buffers. I am just wondering
>>what will happen if i implement this design in altera. I'll have to
>>take all drivers at one place, put a mux and re-route them to all
>>sink. won't it affect timing considerably.
>>considering it xilinx becomes obvious choice because of tri-state
>>buffers n lines. Anyone has any other opinion or observation on the
>>topic??
> 
> 
> On-chip tri-state is pretty near dead.  As metal has gotten slower
> relative to transistors, making a long wire with multiple tri-state
> drivers on it has become very slow, since there's no easy way to
> re-buffer the signal (the signal could be flowing in one of two
> directions, since there are multiple drive points).
> 
> For that reason, all Altera devices have relied on multiplexers to
> make on-chip buses, rather than on-chip tri-states.
> 
> This approach is clearly winning out.  Recently a company (I forget
> the name) filed a patent for SoC designs on ASICs where they use
> multiplexers rather than tri-state buses.  So ASICs are following in
> FPGA footsteps here.  Xilinx has also gradually abandoned on-chip
> tri-states (the 4K had real tri-states, Virtex-2 has a dedicated
> distributed mux, and Spartan-3 gets rid of that and relies on the
> regular logic).  Altera has always used the regular logic approach.
> 
> So don't worry about the lack of on-chip tri-states in Altera devices
> -- muxes are the way to go.  Note that once you're using muxes to
> implement your buses, it also opens up the possibility of using more
> general switching fabrics (in the limit a crossbar) rather than one
> centralized bus.
> 
> Vaughn
> Altera

Is Spartan 3 still faster and less expensive when there are 100+
16/32-bit registers on a bus?

-qlyus


Austin Lesea <austin@xilinx.com> wrote in message news:<c9l1q5$m251@cliff.xsj.xilinx.com>...
> Yup,
> 
> Tristate is actually slower.
> 
> The tristate buffers in Virtex and all subsequent families are in fact 
> separate bidirectional logic structures that simulate the behavior of a 
> tristate bus.
> 
> http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf
> 
> see page 11:  Spartan 3 is faster and less expensive without any 
> tristate elements at all!
> 
> Austin
> 
> rickman wrote:
> > digari wrote:
> > 
> >>hi,
> >>i m still in planning phase of my design. i was just looking at xilinx
> >>and altera devices. Xilinx provides tri-state buffers as well as
> >>tri-state lines whereas altera doesn't and suggests to use muxs
> >>insteed of tri-state buffers.
> >>Now assume that i have a bus in my design where lots of drivers are
> >>there n driving bus through tri-state buffers. I am just wondering
> >>what will happen if i implement this design in altera. I'll have to
> >>take all drivers at one place, put a mux and re-route them to all
> >>sink. won't it affect timing considerably.
> >>considering it xilinx becomes obvious choice because of tri-state
> >>buffers n lines. Anyone has any other opinion or observation on the
> >>topic??
> > 
> > 
> > The older Xilinx chips have lots of tristate buffers.  But they have
> > been phasing them out for the last two generations and have completed
> > that task with the Spartan 3 chips.  The internal tristate buffer is
> > dead!  
> > 
> > BTW, if you think routing signals to a common mux is slow, you should
> > check the timing numbers on the tbufs driving long lines which then run
> > around the chip.  If you do a really good job of placement, you can
> > minimize the speed penalty.  But tristate buffers will *always* be slow
> > due to the nature of a passive pullup.  
> > 
> > Altera has a cascade backbone inside their LABs that will AND the
> > outputs of the LUTs at a very high speed.  This can implement a very
> > wide AND-OR gate for wide muxes at high speed.  
> >

That's hardly a typical application. Also, I'm not sure if there ever were
any FPGAs of any flavour that had longlines with 100+ tristate drivers on
them. You should put those registers in a BlockRam mate!
Cheers, Syms.
"qlyus" <qlyus@yahoo.com> wrote in message
news:da71446f.0406031036.137fd0db@posting.google.com...
> Is Spartan 3 still faster and less expensive when there are 100+
> 16/32-bit registers on a bus?
>
> -qlyus
>
>

With that many registers, you might look at alternative architectures.  If sequential access is
normally used, a shift register works well.  If random access is needed, the troublesome part is
readback.  You might consider readback through a dual port RAM such that the external world has
access to one port and the FPGA internals have access to the other port.

qlyus wrote:

> Is Spartan 3 still faster and less expensive when there are 100+
> 16/32-bit registers on a bus?
>
> -qlyus
>
> Austin Lesea <austin@xilinx.com> wrote in message news:<c9l1q5$m251@cliff.xsj.xilinx.com>...
> > Yup,
> >
> > Tristate is actually slower.
> >
> > The tristate buffers in Virtex and all subsequent families are in fact
> > separate bidirectional logic structures that simulate the behavior of a
> > tristate bus.
> >
> > http://www.xilinx.com/bvdocs/appnotes/xapp466.pdf
> >
> > see page 11:  Spartan 3 is faster and less expensive without any
> > tristate elements at all!
> >
> > Austin
> >
> > rickman wrote:
> > > digari wrote:
> > >
> > >>hi,
> > >>i m still in planning phase of my design. i was just looking at xilinx
> > >>and altera devices. Xilinx provides tri-state buffers as well as
> > >>tri-state lines whereas altera doesn't and suggests to use muxs
> > >>insteed of tri-state buffers.
> > >>Now assume that i have a bus in my design where lots of drivers are
> > >>there n driving bus through tri-state buffers. I am just wondering
> > >>what will happen if i implement this design in altera. I'll have to
> > >>take all drivers at one place, put a mux and re-route them to all
> > >>sink. won't it affect timing considerably.
> > >>considering it xilinx becomes obvious choice because of tri-state
> > >>buffers n lines. Anyone has any other opinion or observation on the
> > >>topic??
> > >
> > >
> > > The older Xilinx chips have lots of tristate buffers.  But they have
> > > been phasing them out for the last two generations and have completed
> > > that task with the Spartan 3 chips.  The internal tristate buffer is
> > > dead!
> > >
> > > BTW, if you think routing signals to a common mux is slow, you should
> > > check the timing numbers on the tbufs driving long lines which then run
> > > around the chip.  If you do a really good job of placement, you can
> > > minimize the speed penalty.  But tristate buffers will *always* be slow
> > > due to the nature of a passive pullup.
> > >
> > > Altera has a cascade backbone inside their LABs that will AND the
> > > outputs of the LUTs at a very high speed.  This can implement a very
> > > wide AND-OR gate for wide muxes at high speed.
> > >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

I always thought the internal tri-state bus in Xilinx was an advantage
over Altera's devices.  I started to use this feature in 4k series, in
which the save of gates in this low density was more obvious when
building a bus with 10+ registers.

I have designed many projects with internal tri-state bus.  The latest
one is the 93-tap FIR filters.  Each coefficient is a 16-bit register.
 With other registers and memory blocks, it is very easy to have the
need of 100+ random access.  The tartget device is a V-II Pro.  The
speed is not an issue as the clock for register access can be separate
from the data stream clock.

With Xilinx abandon of tri-state and Altera not doing it from the
beginning,  i am confused with who was smarter.

If Xilinx gets rid of its unique features (such as SRL and tri-state)
more and more, or Altera offers more features which used to be unique
in Xilinx (Stratix-II started to offer 100+ multiplier), I have to ask
why using Xilinx devices anymore?

-qlyus


Austin Lesea <austin@xilinx.com> wrote in message news:<c9nl06$jdk1@cliff.xsj.xilinx.com>...
> Vaughn,
> 
> Yes, we do agree.  Nice to let folks know that we agree on many things.
> 
> Austin
> 
> Vaughn Betz wrote:
> > digari@dacafe.com (digari) wrote in message news:<e0855517.0406012125.492c4ccf@posting.google.com>...
> > 
> >>hi,
> >>i m still in planning phase of my design. i was just looking at xilinx
> >>and altera devices. Xilinx provides tri-state buffers as well as
> >>tri-state lines whereas altera doesn't and suggests to use muxs
> >>insteed of tri-state buffers.
> >>Now assume that i have a bus in my design where lots of drivers are
> >>there n driving bus through tri-state buffers. I am just wondering
> >>what will happen if i implement this design in altera. I'll have to
> >>take all drivers at one place, put a mux and re-route them to all
> >>sink. won't it affect timing considerably.
> >>considering it xilinx becomes obvious choice because of tri-state
> >>buffers n lines. Anyone has any other opinion or observation on the
> >>topic??
> > 
> > 
> > On-chip tri-state is pretty near dead.  As metal has gotten slower
> > relative to transistors, making a long wire with multiple tri-state
> > drivers on it has become very slow, since there's no easy way to
> > re-buffer the signal (the signal could be flowing in one of two
> > directions, since there are multiple drive points).
> > 
> > For that reason, all Altera devices have relied on multiplexers to
> > make on-chip buses, rather than on-chip tri-states.
> > 
> > This approach is clearly winning out.  Recently a company (I forget
> > the name) filed a patent for SoC designs on ASICs where they use
> > multiplexers rather than tri-state buses.  So ASICs are following in
> > FPGA footsteps here.  Xilinx has also gradually abandoned on-chip
> > tri-states (the 4K had real tri-states, Virtex-2 has a dedicated
> > distributed mux, and Spartan-3 gets rid of that and relies on the
> > regular logic).  Altera has always used the regular logic approach.
> > 
> > So don't worry about the lack of on-chip tri-states in Altera devices
> > -- muxes are the way to go.  Note that once you're using muxes to
> > implement your buses, it also opens up the possibility of using more
> > general switching fabrics (in the limit a crossbar) rather than one
> > centralized bus.
> > 
> > Vaughn
> > Altera

Hi,

> I always thought the internal tri-state bus in Xilinx
> was an advantage over Altera's devices.  I started to
> use this feature in 4k series, in which the save of
> gates in this low density was more obvious when building
> a bus with 10+ registers.

In devices where you are constrained by the number of LUTs,
and not performance, TBUFs are great.  And you can still
code with TBUFs if you want, because the synthesis and
mapping tools can automatically transform those into some
other (logically equivalent) representation.

> With Xilinx abandon of tri-state and Altera not doing it
> from the beginning, i am confused with who was smarter.

I am sure there are at least two answers to this question.

> If Xilinx gets rid of its unique features (such as SRL
> and tri-state) more and more, or Altera offers more
> features which used to be unique in Xilinx (Stratix-II
> started to offer 100+ multiplier), I have to ask why
> using Xilinx devices anymore?

Flame on, dude!
Eric