LFSR in xilinx 13.2

Hi,
I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP
for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000
FPGA.

Does anyone know where i can find it?


regards
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Thu, 15 Sep 2011 14:38:33 -0500, salimbaba wrote:

> Hi,
> I am using xilinx 13.2 for my design synthesis and i want to use xilinx
> IP for LFSR but i cannot find it in core gen. I am using Spartan3
> xc3s4000 FPGA.
> 
> Does anyone know where i can find it?

The actual LFSR description should take two or three lines, and it's not 
the kind of thing that needs superhuman effort to optimize, particularly 
if it's an internal XOR type.

An extern XOR type with a whole lot of taps might benefit from some 
pipelining, but even that shouldn't be too hard.

So maybe they didn't think they needed to bother.

-- 
www.wescottdesign.com

Hi,

Here is the link to online LFSR code generator:

http://outputlogic.com/?page_id=275

Thanks,
Evgeni

"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in message 
news:H7-dnYe-8Nqkye_TnZ2dnUVZ_t-dnZ2d@giganews.com...
> Hi,
> I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP
> for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000
> FPGA.
>
> Does anyone know where i can find it?

http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

On Sep 15, 2:38=A0pm, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
> Hi,
> I am using xilinx 13.2 for my design synthesis and i want to use xilinx I=
P
> for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000
> FPGA.
>
> Does anyone know where i can find it?
>
> regards
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

In all ISE releases you can find example designs.  XAPP211: PN
Generator, is one I authored years ago.  There's a verilog and VHDL
version.  A PN Generator is basically an LFSR.  There should be enough
comments in the code to explain how to infer SRL16s (vs FFs).  Here're
some other docs in case you're interested...

Pseudo-random Noise Generators using SRLs (app note and reference
design):
(http://www.xilinx.com/support/documentation/application_notes/
xapp211.pdf)

HDL Coding for PN Generators:
(http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/
xcell/xl35/xl35_44.pdf)


Good luck,
Mike
www.fpgaace.com