I am doing a small experiment with DCM. I used the coregen to configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. RST is also tied to a pushbutton RESET. Feedback 1x internal is configured, and so does the duty cycle correction. Then I instantiate the module in schematic, and tie all the port to inport and outport apprepriately without any IBUF,OBUF or BUFG primitives. I noticed a extra pin coming out of the DCM: CLKIN_IBUFG_OUT. I implemented the design and downloaded to a xc2vp4 FPGA prototype board. But somehow I can not get CLK0 to come out. CLKIN_IBUFG_OUT is coming out fine. LOCKED is still low. So it is not locking, and that is why CLKO is not coming out. But why? Such a simple design. Someone help. Charles
DCM in Xilinx
Started by ●June 7, 2004
Reply by ●June 8, 20042004-06-08
Never mind. It's a silly mistake on my part. I had RST tied to RST pin on the chip. It should be tied to GND. Deh..... "charles" <czheng@ieee.org> wrote in message news:d2fa3f25.0406071851.5a94c50b@posting.google.com...
Reply by ●June 17, 20042004-06-17
Hi, I had the same problem. I think that the clk0 line is routed through a dedicated clock routing line(global) and cannot be brought out. The reason for this I am not sure of yet. But, there isa work around. U could instantiate the FDDRE ( IOB Double data rate registers) primitive and set the inputs to the 2 ff(s) in such a way that the output mimic the clock exactly. -- Joji John ( nansung444@yahoo.com) "Cogito; ergo sum" " plain text reduces headaches" http://www.angelfire.com/ma3/joji http://geocities.com/nansung444 "charles" <czheng@ieee.org> wrote in message news:d2fa3f25.0406071851.5a94c50b@posting.google.com...> I am doing a small experiment with DCM. I used the coregen to > configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. > RST is also tied to a pushbutton RESET. Feedback 1x internal is > configured, and so does the duty cycle correction. Then I instantiate > the module in schematic, and tie all the port to inport and outport > apprepriately without any IBUF,OBUF or BUFG primitives. I noticed a > extra pin coming out of the DCM: CLKIN_IBUFG_OUT. I implemented the > design and downloaded to a xc2vp4 FPGA prototype board. But somehow I > can not get CLK0 to come out. CLKIN_IBUFG_OUT is coming out fine. > LOCKED is still low. So it is not locking, and that is why CLKO is > not coming out. But why? Such a simple design. Someone help. > > Charles