slice # change from .syr to map report

I was experimenting a coregen generated FFT module.  How come the slice
utilization jump 6 fold from the synthesis report to map report?  XST does
not just synthesis the logic into generic logics, it synthesize the logic to
target resources, right? What I am saying is that if I change the target
device, the # of slice used would change if the architecture of the slice is
different between these two devices.  So why there is such a big change in
the # of slice used (and other resource for that matter) between MAP report
and synthesis report.
I am definitely a newbie, so please bear with me.

Thanks,
Charles

It is a matter of packing.  a slice is counted as used if only one of the two
LUTs is used. It is also used if the slice is used as a route-through.  XST
counts LUTs.  The placer may also be separating the LUTs from a carry chain or
carry chain from flip-flops due to poor mapping.  Look at the design under FPGA
editor (preferably) or under floorplanner to see what it did to the design.

charles wrote:

> I was experimenting a coregen generated FFT module.  How come the slice
> utilization jump 6 fold from the synthesis report to map report?  XST does
> not just synthesis the logic into generic logics, it synthesize the logic to
> target resources, right? What I am saying is that if I change the target
> device, the # of slice used would change if the architecture of the slice is
> different between these two devices.  So why there is such a big change in
> the # of slice used (and other resource for that matter) between MAP report
> and synthesis report.
> I am definitely a newbie, so please bear with me.
>
> Thanks,
> Charles

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