Hi all, I'm using the code below to generate a pulse which is 16x57600 from a 51.2 MHz clock signal to controll the sampling in a rs232 module. The pulse generator does not work however. It generats a constant high signal instead of a 921.6 kHz pulse. Can anyone see what might be faulty with my design? I'm clueless... /Johan library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity baud16 is port( Clk : in std_logic; baud_pulse : out std_logic); end entity baud16; architecture imp of baud16 is attribute BOX_TYPE : string; component SRL16E is -- synthesis translate_off generic ( INIT : bit_vector := X"0000" ); -- synthesis translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic ); end component SRL16E; attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; component FD is port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component FD; attribute BOX_TYPE of FD : component is "BLACK_BOX"; signal clkdv56 : std_logic; signal clkdv56_i1 : std_logic; signal clkdv56_i2 : std_logic; signal clkdv56_i3 : std_logic; -- signal clkdv14_4 : std_logic; signal baud_pulse_i : std_logic; begin --Denna SRL dividerar inklockan med 14 Del_8 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '0', -- [in std_logic] Q => clkdv56_i1); -- [out std_logic] Del_16_1 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i1, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i2); -- [out std_logic] Del_16_2 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i2, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i3); -- [out std_logic] Del_16_3 : SRL16E --synthesis translate_off generic map ( INIT => X"0001") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i3, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56); -- [out std_logic] DFF : FD port map ( C => Clk, -- [in std_logic] D => clkdv56, -- [in std_logic] Q => baud_pulse); -- [out std_logic] end architecture imp;
pulse generation using SRL16E on a Virtex-II
Started by ●June 15, 2004
Reply by ●June 15, 20042004-06-15
"Johan Bernsp�ng" <johbe@foi.se> wrote>Hi all,>I'm using the code below to generate a pulse which is 16x57600 from a >51.2 MHz clock signal to controll the sampling in a rs232 module. The >pulse generator does not work however. It generats a constant high >signal instead of a 921.6 kHz pulse. > >Can anyone see what might be faulty with my design? I'm clueless... > >/JohanHi Johan, the SRL16E components in your design are not initialized for synthesis. Dependent on your synthesis tool, either delete the "synthesis translate_on/off" lines or add attributes with INIT values for the SRL16E components. Hope this helps, Michael
Reply by ●June 15, 20042004-06-15
Tjena Johan, You can't directly connect the output from on SRL16 to the next one. It only works for the first SRL16. The other SRL16 will have it's output high for many clock cycles which creates the constant high signal. For the other SRL16, you need to clean the signal to only be high for one clock cycle. G�ran Bilski Johan Bernsp�ng wrote:> Hi all, > > I'm using the code below to generate a pulse which is 16x57600 from a > 51.2 MHz clock signal to controll the sampling in a rs232 module. The > pulse generator does not work however. It generats a constant high > signal instead of a 921.6 kHz pulse. > > Can anyone see what might be faulty with my design? I'm clueless... > > /Johan > > > library IEEE; > use IEEE.std_logic_1164.all; > > library unisim; > use unisim.vcomponents.all; > > entity baud16 is > port( > Clk : in std_logic; > baud_pulse : out std_logic); > end entity baud16; > > architecture imp of baud16 is > > attribute BOX_TYPE : string; > component SRL16E is > -- synthesis translate_off > generic ( > INIT : bit_vector := X"0000" > ); > -- synthesis translate_on > port ( > CE : in std_logic; > D : in std_logic; > Clk : in std_logic; > A0 : in std_logic; > A1 : in std_logic; > A2 : in std_logic; > A3 : in std_logic; > Q : out std_logic > ); > end component SRL16E; > attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; > > component FD is > port ( > C : in std_logic; > D : in std_logic; > Q : out std_logic); > end component FD; > attribute BOX_TYPE of FD : component is "BLACK_BOX"; > > > signal clkdv56 : std_logic; > signal clkdv56_i1 : std_logic; > signal clkdv56_i2 : std_logic; > signal clkdv56_i3 : std_logic; > -- signal clkdv14_4 : std_logic; > signal baud_pulse_i : std_logic; > begin > > > --Denna SRL dividerar inklockan med 14 > Del_8 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '0', -- [in std_logic] > Q => clkdv56_i1); -- [out std_logic] > > Del_16_1 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i1, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i2); -- [out std_logic] > > Del_16_2 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i2, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i3); -- [out std_logic] > > Del_16_3 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0001") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i3, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56); -- [out std_logic] > > > > DFF : FD > port map ( > C => Clk, -- [in std_logic] > D => clkdv56, -- [in std_logic] > Q => baud_pulse); -- [out std_logic] > > end architecture imp;
Reply by ●June 15, 20042004-06-15
This is a multi-part message in MIME format. --------------070802080207010801070009 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hi, Instead of you spending time creating the code, I have attached some modules. The baud_rate module will produce the signal that you want. The module is however a little more flexible and allows you to specify the ratio that you want to divide the incoming clock. The module will find all the factors between 2-16 which makes up the ratio. The problem is when the ratio is a prim number and thus can't be split up into factors. The module will then return to a standard counter for implementing the function. For some application, the ratio doesn't need to be exact and there are some inaccuracy allowed. UARTs has this flexibility. So you can specify an inaccuracy which allows the modules to search for values around the ratio which can be split into factors. The cleaning of the signal for the SRL16 can be done in a LUT (you need an AND gate) but I have used two DFFs for doing the same function in order to save some LUTs. The code is a good example of what VHDL can do. G�ran Johan Bernsp�ng wrote:> Hi all, > > I'm using the code below to generate a pulse which is 16x57600 from a > 51.2 MHz clock signal to controll the sampling in a rs232 module. The > pulse generator does not work however. It generats a constant high > signal instead of a 921.6 kHz pulse. > > Can anyone see what might be faulty with my design? I'm clueless... > > /Johan > > > library IEEE; > use IEEE.std_logic_1164.all; > > library unisim; > use unisim.vcomponents.all; > > entity baud16 is > port( > Clk : in std_logic; > baud_pulse : out std_logic); > end entity baud16; > > architecture imp of baud16 is > > attribute BOX_TYPE : string; > component SRL16E is > -- synthesis translate_off > generic ( > INIT : bit_vector := X"0000" > ); > -- synthesis translate_on > port ( > CE : in std_logic; > D : in std_logic; > Clk : in std_logic; > A0 : in std_logic; > A1 : in std_logic; > A2 : in std_logic; > A3 : in std_logic; > Q : out std_logic > ); > end component SRL16E; > attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; > > component FD is > port ( > C : in std_logic; > D : in std_logic; > Q : out std_logic); > end component FD; > attribute BOX_TYPE of FD : component is "BLACK_BOX"; > > > signal clkdv56 : std_logic; > signal clkdv56_i1 : std_logic; > signal clkdv56_i2 : std_logic; > signal clkdv56_i3 : std_logic; > -- signal clkdv14_4 : std_logic; > signal baud_pulse_i : std_logic; > begin > > > --Denna SRL dividerar inklockan med 14 > Del_8 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '0', -- [in std_logic] > Q => clkdv56_i1); -- [out std_logic] > > Del_16_1 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i1, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i2); -- [out std_logic] > > Del_16_2 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i2, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i3); -- [out std_logic] > > Del_16_3 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0001") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i3, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56); -- [out std_logic] > > > > DFF : FD > port map ( > C => Clk, -- [in std_logic] > D => clkdv56, -- [in std_logic] > Q => baud_pulse); -- [out std_logic] > > end architecture imp;--------------070802080207010801070009 Content-Type: text/plain; name="baudrate.vhd" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="baudrate.vhd" ------------------------------------------------------------------------------- -- $Id: baudrate.vhd,v 1.2 2003/01/16 22:32:37 tise Exp $ ------------------------------------------------------------------------------- -- baudrate.vhd ------------------------------------------------------------------------------- -- -- *************************************************************************** -- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This text contains proprietary, confidential ** -- ** information of Xilinx, Inc. , is distributed by ** -- ** under license from Xilinx, Inc., and may be used, ** -- ** copied and/or disclosed only pursuant to the terms ** -- ** of a valid license agreement with Xilinx, Inc. ** -- ** ** -- ** Unmodified source code is guaranteed to place and route, ** -- ** function and run at speed according to the datasheet ** -- ** specification. Source code is provided "as-is", with no ** -- ** obligation on the part of Xilinx to provide support. ** -- ** ** -- ** Xilinx Hotline support of source code IP shall only include ** -- ** standard level Xilinx Hotline support, and will only address ** -- ** issues and questions related to the standard released Netlist ** -- ** version of the core (and thus indirectly, the original core source). ** -- ** ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Support Hotline will only be able ** -- ** to confirm the problem in the Netlist version of the core. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: baudrate.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- baudrate.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.2 $ -- Date: $Date: 2003/01/16 22:32:37 $ -- -- History: -- goran 2001-06-12 First Version -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Baud_Rate is generic ( C_USE_FIXED : integer := 1; -- Fixed baudrate C_RATIO : integer := 814; -- The ratio between clk and the asked -- baudrate multiplied with 16 C_INACCURACY : integer := 15 -- The maximum inaccuracy of the clk ); -- division in per thousands port ( Clk : in std_logic; Div_Factor : in std_logic_vector(0 to 15); EN_16x_Baud : out std_logic); end entity Baud_Rate; library unisim; use unisim.all; library opb_uartlite_v2_00_a; use opb_uartlite_v2_00_a.Divide_Part; architecture VHDL_RTL of Baud_Rate is component MUXCY_L is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component MUXCY_L; component XORCY is port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component XORCY; component Divide_Part is generic ( Ratio : natural; First : boolean); port ( Clk : in std_logic; Clk_En : in std_logic; Clk_En_Out : out std_logic); end component Divide_Part; -- log2 function returns the number of bits required to encode x choices function log2(x : natural) return integer is variable i : integer := 0; begin if x = 0 then return 0; else while 2**i < x loop i := i+1; end loop; return i; end if; end function log2; ----------------------------------------------------------------------------- -- Calculate the number of SRL16s needed for the Ratio R ----------------------------------------------------------------------------- constant MAX_DIV_FACTOR : natural := 16; subtype SRL16_DIV_TYPE is natural range 2 to MAX_DIV_FACTOR; type FACTORS_LIST_TYPE is array (natural range 1 to 15) of SRL16_DIV_TYPE; type FACTORS_TYPE is record Good_Divide : boolean; Nr_Of_Factors : natural; Factor_List : FACTORS_LIST_TYPE; end record FACTORS_TYPE; ----------------------------------------------------------------------------- -- Trying to divide R into integer values of values 2-16 until the end result -- is between 2-16. ----------------------------------------------------------------------------- function Get_Factors (R : natural) return FACTORS_TYPE is variable N : natural := R; variable Result : FACTORS_TYPE; variable no : natural := 1; variable Found : boolean; begin -- function Get_Factors if (N < 16) then Result.FACTOR_LIST(1) := N; Result.Nr_Of_Factors := 1; Result.Good_Divide := true; return Result; end if; while N /= 1 loop Found := false; for I in 16 downto 2 loop if ((N mod I = 0)) then -- Found factor Result.FACTOR_LIST(no) := I; N := N / I; no := no + 1; Found := true; exit; end if; end loop; -- I if (not(Found)) then Result.Good_Divide := false; exit; end if; end loop; if (found) then Result.Good_Divide := true; Result.Nr_Of_Factors := no-1; end if; return Result; end function Get_Factors; ----------------------------------------------------------------------------- -- Trying to find a ratio that is within 1.5% of the asked ratio and that the -- ratio can be implemented with SRL16. ----------------------------------------------------------------------------- function Find_Best_Factors (R : natural) return FACTORS_TYPE is constant Proc_Diff : natural := R*C_INACCURACY/1000; -- Calculate the max difference -- for the maximum inaccuracy variable Result : FACTORS_TYPE; begin -- function Find_Best_Factors Result := Get_Factors(R); if (Result.Good_Divide) then return Result; end if; for I in 1 to Proc_Diff loop Result := Get_Factors(R+I); if (Result.Good_Divide) then return Result; end if; Result := Get_Factors(R-I); if (Result.Good_Divide) then return Result; end if; end loop; -- I Result.Good_Divide := false; return Result; end function Find_Best_Factors; constant Divide_Factors : FACTORS_TYPE := Find_Best_Factors(C_RATIO); signal Clk_En_I : std_logic_vector(0 to Divide_Factors.Nr_Of_Factors); signal Count : std_logic_vector(0 to 15); begin -- architecture VHDL_RTL Using_Fixed_Baudrate : if (C_USE_FIXED /= 0) generate ----------------------------------------------------------------------------- -- A clean and good ratio was found that was within the 1.5% limit, so -- implement the uartlite division using SRL16s ----------------------------------------------------------------------------- Using_SRL16s : if (Divide_Factors.Good_Divide) generate Clk_En_I(0) <= '1'; SRL16s : for I in 1 to Divide_Factors.Nr_Of_Factors generate Divide_I : Divide_Part generic map ( Ratio => Divide_Factors.FACTOR_LIST(I), -- [natural range 2 to 16] First => (I = 1)) -- [boolean] port map ( Clk => Clk, -- [in std_logic] Clk_En => Clk_En_I(I-1), -- [in std_logic] Clk_En_Out => Clk_En_I(I)); -- [out std_logic] end generate SRL16s; En_16x_Baud <= Clk_En_I(Divide_Factors.Nr_Of_Factors); end generate Using_SRL16s; ----------------------------------------------------------------------------- -- Couldn't find a good ratio within the 1.5% limit so implement the uartlite -- generation using a standard counter ----------------------------------------------------------------------------- Using_Counter : if (not Divide_Factors.Good_Divide) generate constant Nr_Of_Bits : natural := log2(C_RATIO-1); constant New_Value : std_logic_vector(0 to Nr_Of_Bits-1) := std_logic_vector(to_unsigned(C_RATIO-1, Nr_Of_Bits)); signal Cnt : std_logic_vector(0 to Nr_Of_Bits-1); signal New_Cnt : std_logic_vector(0 to Nr_Of_Bits-1); signal Carry : std_logic_vector(0 to Nr_Of_Bits); signal Count : std_logic_vector(0 to Nr_Of_Bits-1); begin Carry(0) <= '0'; -- Always subracting All_Bits : for I in 0 to Nr_Of_Bits-1 generate New_Cnt(I) <= not(Count(I)) when Carry(Nr_Of_Bits) = '0' else New_Value(I); MUXCY_L_I1 : MUXCY_L port map ( DI => '0', -- [in std_logic] CI => Carry(I), -- [in std_logic] S => New_Cnt(I), -- [in std_logic] LO => Carry(I+1)); -- [out std_logic] XORCY_I1 : XORCY port map ( LI => New_Cnt(I), -- [in std_logic] CI => Carry(I), -- [in std_logic] O => Cnt(I)); -- [out std_logic] end generate All_Bits; Counter : process (Clk) is begin -- process Counter if Clk'event and Clk = '1' then -- rising clock edge Count <= Cnt; end if; end process Counter; En_16x_Baud <= Carry(Nr_Of_Bits); end generate Using_Counter; end generate Using_Fixed_Baudrate; Dynamic_Baudrate: if (C_USE_FIXED = 0) generate Counter : process (Clk) is begin -- process Counter if Clk'event and Clk = '1' then -- rising clock edge if (Count = "0000000000000000") then Count <= Div_Factor; EN_16x_Baud <= '1'; else Count <= std_logic_vector(unsigned(Count) - 1); EN_16x_Baud <= '0'; end if; end if; end process Counter; end generate Dynamic_Baudrate; end architecture VHDL_RTL; --------------070802080207010801070009 Content-Type: text/plain; name="divide_part.vhd" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="divide_part.vhd" ------------------------------------------------------------------------------- -- $Id: divide_part.vhd,v 1.2 2003/02/13 16:13:28 goran Exp $ ------------------------------------------------------------------------------- -- divide_part.vhd - Entity and architecture -- -- *************************************************************************** -- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This text contains proprietary, confidential ** -- ** information of Xilinx, Inc. , is distributed by ** -- ** under license from Xilinx, Inc., and may be used, ** -- ** copied and/or disclosed only pursuant to the terms ** -- ** of a valid license agreement with Xilinx, Inc. ** -- ** ** -- ** Unmodified source code is guaranteed to place and route, ** -- ** function and run at speed according to the datasheet ** -- ** specification. Source code is provided "as-is", with no ** -- ** obligation on the part of Xilinx to provide support. ** -- ** ** -- ** Xilinx Hotline support of source code IP shall only include ** -- ** standard level Xilinx Hotline support, and will only address ** -- ** issues and questions related to the standard released Netlist ** -- ** version of the core (and thus indirectly, the original core source). ** -- ** ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Support Hotline will only be able ** -- ** to confirm the problem in the Netlist version of the core. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: divide_part.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- divide_part.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.2 $ -- Date: $Date: 2003/02/13 16:13:28 $ -- -- History: -- goran 2003-02-13 First Version -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity Divide_part is generic ( Ratio : natural; First : boolean := true ); port ( Clk : in std_logic; Clk_En : in std_logic; Clk_En_Out : out std_logic ); end entity Divide_part; library unisim; use unisim.all; library ieee; use ieee.numeric_std.all; architecture VHDL_RTL of Divide_part is component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000"); -- pragma translate_on port ( Q : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CE : in std_logic; Clk : in std_logic; D : in std_logic ); end component SRL16E; component SRLC16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000"); -- pragma translate_on port ( Q : out std_logic; Q15 : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CE : in std_logic; Clk : in std_logic; D : in std_logic ); end component SRLC16E; signal loop_Bit : std_logic; attribute INIT : string; constant Nr_Of_SRL16 : natural := 1 + ((Ratio-1)/16); constant Last_SRL16_Ratio : natural := ((Ratio-1) mod 16); constant A : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(Last_SRL16_Ratio, 4)); signal shifts : std_logic_vector(0 to Nr_Of_SRL16); signal Emptys : std_logic_vector(0 to Nr_Of_SRL16); begin -- architecture VHDL_RTL One_SRL16 : if (Nr_Of_SRL16 = 1) generate attribute INIT of SRL16E_I : label is "0001"; begin SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate One_SRL16; Two_SRL16 : if (Nr_Of_SRL16 = 2) generate attribute INIT of SRLC16E_1 : label is "0001"; attribute INIT of SRL16E_2 : label is "0000"; begin -- The first SRLC16E SRLC16E_1 : SRLC16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(1), -- [out std_logic] Q => Emptys(1)); -- [out std_logic] SRL16E_2 : SRL16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(1), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate Two_SRL16; More_Than_Two : if (Nr_Of_SRL16 > 2) generate attribute INIT of SRLC16E_1 : label is "0001"; attribute INIT of SRL16E_n : label is "0000"; begin -- The first SRLC16E SRLC16E_1 : SRLC16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(1), -- [out std_logic] Q => Emptys(1)); -- [out std_logic] The_Rest : for I in 2 to Nr_Of_SRL16-2 generate attribute INIT of SRLC16E_I : label is "0000"; begin SRLC16E_I : SRLC16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(I-1), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(I), -- [out std_logic] Q => Emptys(I)); -- [out std_logic] end generate The_Rest; -- The last SRL16 SRL16E_n : SRL16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(Nr_Of_SRL16-2), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate More_Than_Two; ----------------------------------------------------------------------------- -- If the SRL16 is the first in a serie then the output is a clean single -- clock pulse ----------------------------------------------------------------------------- Is_First : if (First) generate Clk_En_Out <= loop_Bit; end generate Is_First; ----------------------------------------------------------------------------- -- If not the first the output has to be masked so that it produce a single -- clock pulse ----------------------------------------------------------------------------- not_First : if (not First) generate signal Out1 : std_logic; begin Out1_DFF : process (Clk) is begin -- process Out1_DFF if Clk'event and Clk = '1' then -- rising clock edge Out1 <= loop_Bit; end if; end process Out1_DFF; Out2_DFF : process (Clk) is begin -- process Out2_DFF if Clk'event and Clk = '1' then -- rising clock edge if (Out1 = '1') then Clk_En_Out <= Clk_En; end if; end if; end process Out2_DFF; end generate not_First; end architecture VHDL_RTL; --------------070802080207010801070009--
Reply by ●June 15, 20042004-06-15
> Instead of you spending time creating the code, I have attached some > modules.Goran, thanks a lot for such an interesting example of VHDL power. I couldn't care less for a baudrate generator, but I liked a lot the way it's handled. Very clever. BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices in a Spartan III. I had to comment out the "library opbxxxx" lines, tough. Thanks again! Have you some other more ? ;-))
Reply by ●June 15, 20042004-06-15
This is a multi-part message in MIME format. --------------080301000601040305090305 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hi, Glad that you liked the code. I think it's showing the power of a programming language like VHDL. Yes, I have more code but that is MicroBlaze and I can't send out that. ;-) G�ran Bilski Antonio Pasini wrote:>>Instead of you spending time creating the code, I have attached some >>modules. >> >> > >Goran, > >thanks a lot for such an interesting example of VHDL power. >I couldn't care less for a baudrate generator, but I liked a lot the way >it's handled. Very clever. > >BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices >in a Spartan III. > >I had to comment out the "library opbxxxx" lines, tough. > >Thanks again! > >Have you some other more ? ;-)) > > > > >--------------080301000601040305090305 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> <meta http-equiv="Content-Type" content="text/html;charset=ISO-8859-1"> <title></title> </head> <body text="#000000" bgcolor="#ffffff"> Hi,<br> <br> Glad that you liked the code. I think it's showing the power of a programming language like VHDL.<br> <br> Yes, I have more code but that is MicroBlaze and I can't send out that. <span class="moz-smiley-s3"><span> ;-) </span></span><br> <br> Göran Bilski<br> <br> Antonio Pasini wrote:<br> <blockquote type="cite" cite="mid1GHzc.473289$rM4.19620138@news4.tin.it"> <blockquote type="cite"> <pre wrap="">Instead of you spending time creating the code, I have attached some modules. </pre> </blockquote> <pre wrap=""><!----> Goran, thanks a lot for such an interesting example of VHDL power. I couldn't care less for a baudrate generator, but I liked a lot the way it's handled. Very clever. BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices in a Spartan III. I had to comment out the "library opbxxxx" lines, tough. Thanks again! Have you some other more ? ;-)) </pre> </blockquote> </body> </html> --------------080301000601040305090305--
Reply by ●June 15, 20042004-06-15
Hey Goran, How about posting the code direct. Not all of us have news hosts that can pass on attachments! Ta, Syms.
Reply by ●June 15, 20042004-06-15
Symon wrote:> Hey Goran, > How about posting the code direct. Not all of us have news hosts that can > pass on attachments! > Ta, Syms...or maybe a couple of links into a Xilinx.com\comp.arch.fpga.Date.ID.YGTI.. one link could be vanilla text, and one html syntax highlighted (many editors now have a save-as html option), and you can also copy/paste from a web browser into a text editor, and keep just the code. This also allows bookmarking, and avoids anyone bleating about bandwidth usage... I presume everyone can web-link from their news readers OK ? -jg
Reply by ●June 15, 20042004-06-15
On Tue, 15 Jun 2004 15:21:50 -0700, "Symon" <symon_brewer@hotmail.com> wrote:>Hey Goran, >How about posting the code direct. Not all of us have news hosts that can >pass on attachments! >Ta, Syms.Or, just wait till the end of the month when it will turn up in the archive at www.fpga-faq.com Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COM
Reply by ●June 16, 20042004-06-16
Ok, Here is the two files inlined. G�ran ------------------------------------------------------------------------------- -- $Id: divide_part.vhd,v 1.2 2003/02/13 16:13:28 goran Exp $ ------------------------------------------------------------------------------- -- divide_part.vhd - Entity and architecture -- -- *************************************************************************** -- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This text contains proprietary, confidential ** -- ** information of Xilinx, Inc. , is distributed by ** -- ** under license from Xilinx, Inc., and may be used, ** -- ** copied and/or disclosed only pursuant to the terms ** -- ** of a valid license agreement with Xilinx, Inc. ** -- ** ** -- ** Unmodified source code is guaranteed to place and route, ** -- ** function and run at speed according to the datasheet ** -- ** specification. Source code is provided "as-is", with no ** -- ** obligation on the part of Xilinx to provide support. ** -- ** ** -- ** Xilinx Hotline support of source code IP shall only include ** -- ** standard level Xilinx Hotline support, and will only address ** -- ** issues and questions related to the standard released Netlist ** -- ** version of the core (and thus indirectly, the original core source). ** -- ** ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Support Hotline will only be able ** -- ** to confirm the problem in the Netlist version of the core. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: divide_part.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- divide_part.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.2 $ -- Date: $Date: 2003/02/13 16:13:28 $ -- -- History: -- goran 2003-02-13 First Version -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity Divide_part is generic ( Ratio : natural; First : boolean := true ); port ( Clk : in std_logic; Clk_En : in std_logic; Clk_En_Out : out std_logic ); end entity Divide_part; library unisim; use unisim.all; library ieee; use ieee.numeric_std.all; architecture VHDL_RTL of Divide_part is component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000"); -- pragma translate_on port ( Q : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CE : in std_logic; Clk : in std_logic; D : in std_logic ); end component SRL16E; component SRLC16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000"); -- pragma translate_on port ( Q : out std_logic; Q15 : out std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; CE : in std_logic; Clk : in std_logic; D : in std_logic ); end component SRLC16E; signal loop_Bit : std_logic; attribute INIT : string; constant Nr_Of_SRL16 : natural := 1 + ((Ratio-1)/16); constant Last_SRL16_Ratio : natural := ((Ratio-1) mod 16); constant A : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(Last_SRL16_Ratio, 4)); signal shifts : std_logic_vector(0 to Nr_Of_SRL16); signal Emptys : std_logic_vector(0 to Nr_Of_SRL16); begin -- architecture VHDL_RTL One_SRL16 : if (Nr_Of_SRL16 = 1) generate attribute INIT of SRL16E_I : label is "0001"; begin SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate One_SRL16; Two_SRL16 : if (Nr_Of_SRL16 = 2) generate attribute INIT of SRLC16E_1 : label is "0001"; attribute INIT of SRL16E_2 : label is "0000"; begin -- The first SRLC16E SRLC16E_1 : SRLC16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(1), -- [out std_logic] Q => Emptys(1)); -- [out std_logic] SRL16E_2 : SRL16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(1), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate Two_SRL16; More_Than_Two : if (Nr_Of_SRL16 > 2) generate attribute INIT of SRLC16E_1 : label is "0001"; attribute INIT of SRL16E_n : label is "0000"; begin -- The first SRLC16E SRLC16E_1 : SRLC16E -- pragma translate_off generic map ( INIT => X"0001") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => loop_Bit, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(1), -- [out std_logic] Q => Emptys(1)); -- [out std_logic] The_Rest : for I in 2 to Nr_Of_SRL16-2 generate attribute INIT of SRLC16E_I : label is "0000"; begin SRLC16E_I : SRLC16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(I-1), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q15 => shifts(I), -- [out std_logic] Q => Emptys(I)); -- [out std_logic] end generate The_Rest; -- The last SRL16 SRL16E_n : SRL16E -- pragma translate_off generic map ( INIT => X"0000") -- [bit_vector] -- pragma translate_on port map ( CE => Clk_En, -- [in std_logic] D => shifts(Nr_Of_SRL16-2), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => A(0), -- [in std_logic] A1 => A(1), -- [in std_logic] A2 => A(2), -- [in std_logic] A3 => A(3), -- [in std_logic] Q => loop_Bit); -- [out std_logic] end generate More_Than_Two; ----------------------------------------------------------------------------- -- If the SRL16 is the first in a serie then the output is a clean single -- clock pulse ----------------------------------------------------------------------------- Is_First : if (First) generate Clk_En_Out <= loop_Bit; end generate Is_First; ----------------------------------------------------------------------------- -- If not the first the output has to be masked so that it produce a single -- clock pulse ----------------------------------------------------------------------------- not_First : if (not First) generate signal Out1 : std_logic; begin Out1_DFF : process (Clk) is begin -- process Out1_DFF if Clk'event and Clk = '1' then -- rising clock edge Out1 <= loop_Bit; end if; end process Out1_DFF; Out2_DFF : process (Clk) is begin -- process Out2_DFF if Clk'event and Clk = '1' then -- rising clock edge if (Out1 = '1') then Clk_En_Out <= Clk_En; end if; end if; end process Out2_DFF; end generate not_First; end architecture VHDL_RTL; ------------------------------------------------------------------------------- -- $Id: baudrate.vhd,v 1.2 2003/01/16 22:32:37 tise Exp $ ------------------------------------------------------------------------------- -- baudrate.vhd ------------------------------------------------------------------------------- -- -- *************************************************************************** -- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This text contains proprietary, confidential ** -- ** information of Xilinx, Inc. , is distributed by ** -- ** under license from Xilinx, Inc., and may be used, ** -- ** copied and/or disclosed only pursuant to the terms ** -- ** of a valid license agreement with Xilinx, Inc. ** -- ** ** -- ** Unmodified source code is guaranteed to place and route, ** -- ** function and run at speed according to the datasheet ** -- ** specification. Source code is provided "as-is", with no ** -- ** obligation on the part of Xilinx to provide support. ** -- ** ** -- ** Xilinx Hotline support of source code IP shall only include ** -- ** standard level Xilinx Hotline support, and will only address ** -- ** issues and questions related to the standard released Netlist ** -- ** version of the core (and thus indirectly, the original core source). ** -- ** ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Support Hotline will only be able ** -- ** to confirm the problem in the Netlist version of the core. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: baudrate.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- baudrate.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.2 $ -- Date: $Date: 2003/01/16 22:32:37 $ -- -- History: -- goran 2001-06-12 First Version -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Baud_Rate is generic ( C_USE_FIXED : integer := 1; -- Fixed baudrate C_RATIO : integer := 814; -- The ratio between clk and the asked -- baudrate multiplied with 16 C_INACCURACY : integer := 15 -- The maximum inaccuracy of the clk ); -- division in per thousands port ( Clk : in std_logic; Div_Factor : in std_logic_vector(0 to 15); EN_16x_Baud : out std_logic); end entity Baud_Rate; library unisim; use unisim.all; library opb_uartlite_v2_00_a; use opb_uartlite_v2_00_a.Divide_Part; architecture VHDL_RTL of Baud_Rate is component MUXCY_L is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component MUXCY_L; component XORCY is port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component XORCY; component Divide_Part is generic ( Ratio : natural; First : boolean); port ( Clk : in std_logic; Clk_En : in std_logic; Clk_En_Out : out std_logic); end component Divide_Part; -- log2 function returns the number of bits required to encode x choices function log2(x : natural) return integer is variable i : integer := 0; begin if x = 0 then return 0; else while 2**i < x loop i := i+1; end loop; return i; end if; end function log2; ----------------------------------------------------------------------------- -- Calculate the number of SRL16s needed for the Ratio R ----------------------------------------------------------------------------- constant MAX_DIV_FACTOR : natural := 16; subtype SRL16_DIV_TYPE is natural range 2 to MAX_DIV_FACTOR; type FACTORS_LIST_TYPE is array (natural range 1 to 15) of SRL16_DIV_TYPE; type FACTORS_TYPE is record Good_Divide : boolean; Nr_Of_Factors : natural; Factor_List : FACTORS_LIST_TYPE; end record FACTORS_TYPE; ----------------------------------------------------------------------------- -- Trying to divide R into integer values of values 2-16 until the end result -- is between 2-16. ----------------------------------------------------------------------------- function Get_Factors (R : natural) return FACTORS_TYPE is variable N : natural := R; variable Result : FACTORS_TYPE; variable no : natural := 1; variable Found : boolean; begin -- function Get_Factors if (N < 16) then Result.FACTOR_LIST(1) := N; Result.Nr_Of_Factors := 1; Result.Good_Divide := true; return Result; end if; while N /= 1 loop Found := false; for I in 16 downto 2 loop if ((N mod I = 0)) then -- Found factor Result.FACTOR_LIST(no) := I; N := N / I; no := no + 1; Found := true; exit; end if; end loop; -- I if (not(Found)) then Result.Good_Divide := false; exit; end if; end loop; if (found) then Result.Good_Divide := true; Result.Nr_Of_Factors := no-1; end if; return Result; end function Get_Factors; ----------------------------------------------------------------------------- -- Trying to find a ratio that is within 1.5% of the asked ratio and that the -- ratio can be implemented with SRL16. ----------------------------------------------------------------------------- function Find_Best_Factors (R : natural) return FACTORS_TYPE is constant Proc_Diff : natural := R*C_INACCURACY/1000; -- Calculate the max difference -- for the maximum inaccuracy variable Result : FACTORS_TYPE; begin -- function Find_Best_Factors Result := Get_Factors(R); if (Result.Good_Divide) then return Result; end if; for I in 1 to Proc_Diff loop Result := Get_Factors(R+I); if (Result.Good_Divide) then return Result; end if; Result := Get_Factors(R-I); if (Result.Good_Divide) then return Result; end if; end loop; -- I Result.Good_Divide := false; return Result; end function Find_Best_Factors; constant Divide_Factors : FACTORS_TYPE := Find_Best_Factors(C_RATIO); signal Clk_En_I : std_logic_vector(0 to Divide_Factors.Nr_Of_Factors); signal Count : std_logic_vector(0 to 15); begin -- architecture VHDL_RTL Using_Fixed_Baudrate : if (C_USE_FIXED /= 0) generate ----------------------------------------------------------------------------- -- A clean and good ratio was found that was within the 1.5% limit, so -- implement the uartlite division using SRL16s ----------------------------------------------------------------------------- Using_SRL16s : if (Divide_Factors.Good_Divide) generate Clk_En_I(0) <= '1'; SRL16s : for I in 1 to Divide_Factors.Nr_Of_Factors generate Divide_I : Divide_Part generic map ( Ratio => Divide_Factors.FACTOR_LIST(I), -- [natural range 2 to 16] First => (I = 1)) -- [boolean] port map ( Clk => Clk, -- [in std_logic] Clk_En => Clk_En_I(I-1), -- [in std_logic] Clk_En_Out => Clk_En_I(I)); -- [out std_logic] end generate SRL16s; En_16x_Baud <= Clk_En_I(Divide_Factors.Nr_Of_Factors); end generate Using_SRL16s; ----------------------------------------------------------------------------- -- Couldn't find a good ratio within the 1.5% limit so implement the uartlite -- generation using a standard counter ----------------------------------------------------------------------------- Using_Counter : if (not Divide_Factors.Good_Divide) generate constant Nr_Of_Bits : natural := log2(C_RATIO-1); constant New_Value : std_logic_vector(0 to Nr_Of_Bits-1) := std_logic_vector(to_unsigned(C_RATIO-1, Nr_Of_Bits)); signal Cnt : std_logic_vector(0 to Nr_Of_Bits-1); signal New_Cnt : std_logic_vector(0 to Nr_Of_Bits-1); signal Carry : std_logic_vector(0 to Nr_Of_Bits); signal Count : std_logic_vector(0 to Nr_Of_Bits-1); begin Carry(0) <= '0'; -- Always subracting All_Bits : for I in 0 to Nr_Of_Bits-1 generate New_Cnt(I) <= not(Count(I)) when Carry(Nr_Of_Bits) = '0' else New_Value(I); MUXCY_L_I1 : MUXCY_L port map ( DI => '0', -- [in std_logic] CI => Carry(I), -- [in std_logic] S => New_Cnt(I), -- [in std_logic] LO => Carry(I+1)); -- [out std_logic] XORCY_I1 : XORCY port map ( LI => New_Cnt(I), -- [in std_logic] CI => Carry(I), -- [in std_logic] O => Cnt(I)); -- [out std_logic] end generate All_Bits; Counter : process (Clk) is begin -- process Counter if Clk'event and Clk = '1' then -- rising clock edge Count <= Cnt; end if; end process Counter; En_16x_Baud <= Carry(Nr_Of_Bits); end generate Using_Counter; end generate Using_Fixed_Baudrate; Dynamic_Baudrate: if (C_USE_FIXED = 0) generate Counter : process (Clk) is begin -- process Counter if Clk'event and Clk = '1' then -- rising clock edge if (Count = "0000000000000000") then Count <= Div_Factor; EN_16x_Baud <= '1'; else Count <= std_logic_vector(unsigned(Count) - 1); EN_16x_Baud <= '0'; end if; end if; end process Counter; end generate Dynamic_Baudrate; end architecture VHDL_RTL; Symon wrote:>Hey Goran, >How about posting the code direct. Not all of us have news hosts that can >pass on attachments! >Ta, Syms. > > > >
