Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am facing is that one of the bytes in the packet randomly gets corrupt after a while.. First the packet drop was very frequent at high speeds, then i checked the power requirements of my PHYs and got to know that my regulator couldn't source that much current. Then i changed the regulator and now the problem occurs very rarely or it doesnt occur at all. I have some checks in the RTL to identify if the error is FCS or buffer overflow.So every time the packet drops, my fcs flag is raised. So i viewed the incoming packet and saw that it always had some random corrupt byte. Like i was sending packets with known pattern, so after a while some random byte is getting corrupt. I don't know what to look for from now onwards. I thought maybe it was the heat issue so used heat gun but nah it wasn't the heat problem. My ground noise is 80mv peak-to-peak. Need some pointers.. Regards --------------------------------------- Posted through http://www.FPGARelated.com
gigabit ethernet problem
Started by ●September 22, 2011
Reply by ●February 19, 20122012-02-19
hi have your problem solved, cause i 'm facing the same problem with Realtek RTL8201 chip at the receive section,i connected RXD to TXD and RXDV to TXE to test the chip in loopback through fpga xilinx spartan 3 xc3s400, in this test i got 4 out of 50 packets with fcs error at the pc. what's the issue? tnx for any help>Hi, >I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 >national Gigabit PHYs. So i receive a packet from phy A and transmit itto>PHY B and vice versa. Now the problem i am facing is that one of thebytes>in the packet randomly gets corrupt after a while.. > >First the packet drop was very frequent at high speeds, then i checkedthe>power requirements of my PHYs and got to know that my regulator couldn't >source that much current. Then i changed the regulator and now theproblem>occurs very rarely or it doesnt occur at all. > >I have some checks in the RTL to identify if the error is FCS or buffer >overflow.So every time the packet drops, my fcs flag is raised. So iviewed>the incoming packet and saw that it always had some random corrupt byte. >Like i was sending packets with known pattern, so after a while somerandom>byte is getting corrupt. I don't know what to look for from now onwards. >I thought maybe it was the heat issue so used heat gun but nah it wasn't >the heat problem. >My ground noise is 80mv peak-to-peak. > >Need some pointers.. > >Regards > > >--------------------------------------- >Posted through http://www.FPGARelated.com >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●February 20, 20122012-02-20
On 22/09/2011 20:21, salimbaba wrote:> Hi, > I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 > national Gigabit PHYs. So i receive a packet from phy A and transmit it to > PHY B and vice versa. Now the problem i am facing is that one of the bytes > in the packet randomly gets corrupt after a while.. > > First the packet drop was very frequent at high speeds, then i checked the > power requirements of my PHYs and got to know that my regulator couldn't > source that much current. Then i changed the regulator and now the problem > occurs very rarely or it doesnt occur at all. > > I have some checks in the RTL to identify if the error is FCS or buffer > overflow.So every time the packet drops, my fcs flag is raised. So i viewed > the incoming packet and saw that it always had some random corrupt byte. > Like i was sending packets with known pattern, so after a while some random > byte is getting corrupt. I don't know what to look for from now onwards. > I thought maybe it was the heat issue so used heat gun but nah it wasn't > the heat problem. > My ground noise is 80mv peak-to-peak. > > Need some pointers.. > > Regards > > > --------------------------------------- > Posted through http://www.FPGARelated.comCan you please describe the hardware setup in more detail - is it your own board or a known good board. Has this hardware setup ever worked (ie been error free ?). Is there any pattern in the 'random' corruption (eg is it always bit 0 or a 1 seen as 0 (or a 0 seen as 1) etc etc. Is it always the nth byte in a packet etc. Michael Kellett
Reply by ●February 21, 20122012-02-21
i designed and rout the pcb board,i have one RTL8201BL as lan phy layer and Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't have any error in sending packets, i tested transmit section at 95% bandwidth without a packet loss, but at receive there are random error receiving packets. the bytes that are corrupt are also random and does not have a pattern. only when the packet length become large(about 1400 Bytes), the error occur more frequent about (3-4 out of 20 packets), i don't know how i can debug the problem, tnx in advanced for help :) --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●February 21, 20122012-02-21
On 21/02/2012 05:04, nba83 wrote:> i designed and rout the pcb board,i have one RTL8201BL as lan phy layer and > Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't > have any error in sending packets, i tested transmit section at 95% > bandwidth without a packet loss, but at receive there are random error > receiving packets. the bytes that are corrupt are also random and does not > have a pattern. only when the packet length become large(about 1400 Bytes), > the error occur more frequent about (3-4 out of 20 packets), > i don't know how i can debug the problem, > tnx in advanced for help :) > > > > --------------------------------------- > Posted through http://www.FPGARelated.comI can only make the most general suggestions. How are you generating the test packets - are you sure they are good. Can you check the signal integrity on either side of the PHY. Are the errors similar to those you got when the power supply was poor. Is the position of the errored byte at the start or end of the packet or just anywhere. Do you ever get more than one error per packet. Does it get worse or better with any boundary cases: ie does it never fail with a minimum length packet or fail lots more often with maximum length. Is there any sensitivity to packet contents. Is there any sensitivity to rate of packets. MK
Reply by ●February 21, 20122012-02-21
On Feb 20, 9:04=A0pm, "nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:> i designed and rout the pcb board,i have one RTL8201BL as lan phy layer a=nd> Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't > have any error in sending packets, i tested transmit section at 95% > bandwidth without a packet loss, but at receive there are random error > receiving packets. the bytes that are corrupt are also random and does no=t> have a pattern. only when the packet length become large(about 1400 Bytes=),> the error occur more frequent about (3-4 out of 20 packets), > i don't know how i can debug the problem, > tnx in advanced for help :) > > --------------------------------------- > Posted throughhttp://www.FPGARelated.comHave you checked all your timing? Making setup/hold times for the Rx side of GigE can be tough with a Spartan. Been there, done that, you need to be very careful. John P
Reply by ●February 21, 20122012-02-21
>On Feb 20, 9:04=A0pm, "nba83" ><nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: >> i designed and rout the pcb board,i have one RTL8201BL as lan phy layera=>nd >> Xilinx Spartan 3 XC3s400 as controller. i transmit raw packets. i don't >> have any error in sending packets, i tested transmit section at 95% >> bandwidth without a packet loss, but at receive there are random error >> receiving packets. the bytes that are corrupt are also random and doesno=>t >> have a pattern. only when the packet length become large(about 1400Bytes=>), >> the error occur more frequent about (3-4 out of 20 packets), >> i don't know how i can debug the problem, >> tnx in advanced for help :) >> >> --------------------------------------- >> Posted throughhttp://www.FPGARelated.com > >Have you checked all your timing? Making setup/hold times for the Rx >side of GigE can be tough with a Spartan. Been there, done that, you >need to be very careful. > >John P >no i don't know how to do that? i don't know what are setup/hold times for Rx, and my Phy layer is 100MHz not Gig, I used RTL8201BL and i wrote a simple loopback program in which i connected RXDV to TXE and RXD to TXD at the corresponding TXCLK and RXCLK, do i need to do some timing for this simple program?? here is my code: always @ (posedge RTL_RXCLK) begin data <= RTL_RXD; en <= RTL_RXDV; end always @ (posedge RTL_TXCLK) begin RTL_TXD_I <= data; RTL_TXE_I <= en; end --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●February 22, 20122012-02-22
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com...> here is my code: > > always @ (posedge RTL_RXCLK) > begin > data <= RTL_RXD; > en <= RTL_RXDV; > end > > always @ (posedge RTL_TXCLK) > begin > RTL_TXD_I <= data; > RTL_TXE_I <= en; > endHuh? I havent been reading this thread in details, but how are these clocks syncronized? Maybe they arent, hence your problem.
Reply by ●February 22, 20122012-02-22
>"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message >news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com... >> here is my code: >> >> always @ (posedge RTL_RXCLK) >> begin >> data <= RTL_RXD; >> en <= RTL_RXDV; >> end >> >> always @ (posedge RTL_TXCLK) >> begin >> RTL_TXD_I <= data; >> RTL_TXE_I <= en; >> end > >Huh? I havent been reading this thread in details, but how are theseclocks>syncronized? Maybe they arent, hence your problem. > > > >i write it in two processes to ensure if the two clk are not syncronized the data won't read and transmited bad. --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●February 22, 20122012-02-22
"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message news:dtKdneQMFslBK9nSnZ2dnUVZ_hudnZ2d@giganews.com...> >"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message >>news:H5qdnQ4pDqAm-tnSnZ2dnUVZ_q-dnZ2d@giganews.com... >>> here is my code: >>> >>> always @ (posedge RTL_RXCLK) >>> begin >>> data <= RTL_RXD; >>> en <= RTL_RXDV; >>> end >>> >>> always @ (posedge RTL_TXCLK) >>> begin >>> RTL_TXD_I <= data; >>> RTL_TXE_I <= en; >>> end >> >>Huh? I havent been reading this thread in details, but how are these > clocks >>syncronized? Maybe they arent, hence your problem. >> >> >> >> > i write it in two processes to ensure if the two clk are not syncronized > the data won't read and transmited bad.So you are trying to send some data grabbed in one clock domain into a different? You know that will fail? If the clocks are almost similar, it will work for periods when the clock phases are close. If txclk is derived from rxclk, you may get it to work, but first make a common domain.
